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    • 32. 发明公开
    • Cross coupled current regulator
    • Kreuzgekoppelter Stromregler。
    • EP0202603A2
    • 1986-11-26
    • EP86106586.0
    • 1986-05-15
    • ALLEN-BRADLEY COMPANY, INC.
    • Kerkman, Russel J.Rowan, Timothy M.
    • H02M7/5387H02M7/48
    • H02M7/48
    • A current regulator for a variable frequency power supply includes a proportional (51q; 51d ) plus integral circuit (52q, 53q; 52 d ; 53 d ) that produces a composite control output signal (5; 6) for each phase. To improve the performance of the current regulator at higher frequencies, the composite control output signal for each phase also includes a cross coupled component (55q, 56q ; 55 d , 56 d ) which is produced by multiplying a d.c. signal (10) proportional to frequency times an integrator (53q; 53 d ) output signal from another phase. The composite control signals (5; 6) are applied to a voltage source inverter which produces the output currents to a load.
    • 用于可变频率电源的电流调节器包括为每个相产生复合控制输出信号(5; 6)的比例(51q; 51d)加积分电路(52q,53q; 52d; 53d)。 为了提高电流调节器在较高频率下的性能,每相的复合控制输出信号还包括一个交叉耦合的组件(例如,56q; 55d,56d)。 与频率成比例的信号(10)乘以积分器(53q; 53d)从另一相输出信号。 复合控制信号(5; 6)被施加到向负载产生输出电流的电压源逆变器。
    • 36. 发明公开
    • Circuit board having a window adapted to receive a single in-line package module
    • 印刷电路板具有开口,用于在单列直插式封装接收模块
    • EP0766507A1
    • 1997-04-02
    • EP96100333.2
    • 1996-01-11
    • ALLEN-BRADLEY COMPANY, INC.
    • Woychik, Gerard A.
    • H05K3/36
    • H05K3/366H05K3/3442H05K3/403H05K2201/048H05K2201/09036H05K2201/09181H05K2201/09645
    • A mounting (43) for a solderable component module (SCM™) interconnect module (20) includes an elongated aperture (40') or trench (40) or a blind via for receiving an edge (29) of the module (20). The module (20) can be a circuit board or other electrical device and can include edge finger connectors (24, 26, 28). The elongated trench (40) includes hemicylinders (49) located about the periphery. The hemicylinders (49) provide plated through conductors for connecting to the finger connectors (24, 26, 28) of the module. The trench (40) is made according to a method in which the aperture (40') is etched in order to remove barbs or extra copper material caused by milling the aperture (40'). Preferably, the module (20) fits into the trench (40) with an interference or size-on-size fit. The trench (40) may include strain relief areas (94, 96). Additionally, the mounting can include apertures (170, 178) for receiving legs (158, 168) on the mounted board (175).
    • 的安装(43),用于可焊接的部件模块(SCM TM)的互连模块(20)包括在细长孔(40“)或沟槽(40)或经由用于接收在所述模块(20)的边缘(29)的盲。 所述模块(20)可以是一个电路板或其它电气装置,并且可以包括边缘指状连接器(24,26,28)。 细长沟槽(40)包括位于围绕周边hemicylinders(49)。 所述hemicylinders(49)提供穿过导线,用于连接到所述模块的连接器的手指(24,26,28)进行电镀。 沟槽(40)被雅丁制成于其中的孔(40“),以便进行蚀刻,以除去由研磨孔(40引起倒钩或提取铜材料”)的方法。 优选地,所述模块(20)配合到所述沟槽(40),在干扰或尺寸上尺寸配合。 沟槽(40)可以包括应力释放区域(94,96)。 此外,安装可以包括孔径(170,178),用于接收腿(158,168)安装在板(175)。
    • 39. 发明公开
    • Flash memory circuit and method of operation
    • 闪存电路和操作方法
    • EP0542205A3
    • 1995-05-24
    • EP92119230.8
    • 1992-11-11
    • ALLEN-BRADLEY COMPANY, INC.
    • Cowles, Kenneth R.Green, Alex D.Duewiger, Mark J.
    • G11C16/06
    • G11C7/1027G11C7/1045G11C16/08G11C16/26
    • A memory circuit (55) for storing words of data has two memory banks (71; 72) each formed by a plurality of memory devices (73, 74, 75, 76; 77, 78, 79, 80) connected in parallel. In a first mode, the memory circuit (55) responds to an initial request for access and an address signal by reading data from a storage location in one of said memory banks (71; 72). Subsequent requests for access to contiguous storage locations do not require an address signal, instead a control mechanism responds by generating an address to read data alternately from storage locations in the first and second memory banks (71; 72). In a second mode, the memory circuit (55) responds to every request for access to the memory circuit (55) by enabling access to the first or second memory bank (71; 72) as indicated by an address which accompanied the request. The memory devices (73, 74, 75, 76; 77, 78, 79, 80) of a given bank (71; 72) are erased and programmed in parallel. However, when a given storage location is found to contain one or more bits that were not erased, another erase command is sent to only those memory devices (73, 74, 75, 76; 77, 78, 79, 80) associated with a bit that was not erased. Similarly, when a word of data has not been stored properly, only those memory devices which failed to store a bit are placed into the write state for another programming attempt.
    • 用于存储数据字的存储器电路(55)具有两个存储体(71; 72),每个存储体由并行连接的多个存储器件(73,74,75,76; 77,78,79,80)形成。 在第一模式中,存储器电路(55)通过从所述存储体(71; 72)之一中的存储位置读取数据来响应初始的访问请求和地址信号。 后续访问连续存储位置的请求不需要地址信号,而是控制机制通过生成地址以交替地从第一和第二存储体(71; 72)中的存储位置读取数据来响应。 在第二模式中,存储器电路(55)响应访问存储器电路(55)的每个请求,通过允许访问第一或第二存储体(71; 72),如伴随该请求的地址所指示的。 给定库(71; 72)的存储器设备(73,74,75,76; 77,78,79,80)被并行擦除和编程。 然而,当发现给定的存储位置包含一个或多个未被擦除的位时,则另一个擦除命令仅被发送到与存储器相关联的那些存储器设备(73,74,75,76; 77,78,79,80) 未擦除的位。 类似地,当一个数据字未被正确存储时,只有那些未能存储一位的存储器才被置于写入状态以进行另一编程尝试。