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21. 发明公开

EP4284142A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-实审
公开(公告)号：EP4284142A1
公开(公告)日：2023-11-29
申请号：EP23165716.4
申请日：2023-03-30
申请人： Samsung Electronics Co., Ltd.
发明人： CHOI, Moo Rym , SUNG, Jung Tae , JANG, Yun Sun
IPC分类号： H10B41/27 , H10B43/27
摘要： Provided are a memory device, a method of fabricating the same, and an electronic system including the same. The memory device includes a peripheral circuit structure and a cell structure on the peripheral circuit structure. The cell structure comprises a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and having a first conductivity type, gate electrodes on the first surface of the cell substrate, a channel structure intersecting the gate electrodes and connected to the cell substrate, a first impurity region that is in the cell substrate adjacent to the second surface and has a second conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate.

22. 发明公开

EP4231802A1 NON-VOLATILE MEMORY DEVICE 审中-实审
公开(公告)号：EP4231802A1
公开(公告)日：2023-08-23
申请号：EP23155349.6
申请日：2023-02-07
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Seungyeon , BYEON, Daeseok
IPC分类号： H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
摘要： A non-volatile memory device includes a first semiconductor layer including a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, , wherein the first memory cell array and the second memory cell array each include a plurality of word lines, a plurality of memory cells, and a plurality of bit lines, and a second semiconductor layer including a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, , wherein the page buffer circuit region overlaps a boundary region between the first cell region and the second cell region when viewed from the vertical direction.

23. 发明公开

EP4225005A2 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-实审
公开(公告)号：EP4225005A2
公开(公告)日：2023-08-09
申请号：EP22213848.9
申请日：2022-12-15
申请人： Samsung Electronics Co., Ltd.
发明人： KWON, Donghoon , YOON, Boun , JANG, Kihoon
IPC分类号： H10B41/27 , H10B43/27
摘要： A semiconductor device includes a peripheral circuit structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element, and a peripheral insulating structure on the circuit element, a memory cell structure including gate electrodes on the peripheral circuit structure and spaced apart from each other in a stack formation, an upper wiring, and a through-contact plug electrically connecting the upper wiring to an upper connection pattern in, which is in an uppermost position of the connection patterns relative to an upper surface of the substrate providing a base reference surface, wherein the peripheral circuit structure further includes a dam structure on the upper connection pattern, the peripheral insulating structure includes a first insulating layer on the circuit element and a side surface of the upper connection pattern and a second insulating layer, a capping layer, and a third insulating layer sequentially stacked on the first insulating layer, wherein the dam structure passes through the second insulating layer and contacts the upper connection pattern, and wherein the through-contact plug includes a lower portion passing through the dam structure and contacting the upper connection pattern and an upper portion on the lower portion.

24. 发明公开

EP4167701A1 3D CIRCUIT STRUCTURE WITH STAIRSTEP CONTACT CONFIGURATION 审中-实审
公开(公告)号：EP4167701A1
公开(公告)日：2023-04-19
申请号：EP22170773.0
申请日：2022-04-29
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Wu, Meng-Yen , Yeh, Teng-Hao
IPC分类号： H10B41/10 , H10B43/10 , H10B41/50 , H10B41/27 , H10B43/50 , H10B43/27
摘要： Circuit structures to improve manufacturing yield in complex 3D circuits have a first stack of conductors and a second stack of conductors having memory regions and contact regions. Conductors of the first stack have stepped arrangement in the contact region to provide landing areas on the conductors. Connecting circuits connect the landing areas of conductive layers in the first stack to through-stack conductors in vias in the second stack, to connect to circuitry below the stack. The memory regions include arrays of vertical memory pillars. The connecting circuits include interlayer connectors contacting landing areas in the first stack, extending to patterned conductors over the first and second stacks. The patterned conductors can include links from interlayer connectors of the first stack to through-stack connectors of the second stack. The circuit structure can include a plurality of structural vertical pillars in the contact region of the first stack.

25. 发明公开

EP4164357A1 SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4164357A1
公开(公告)日：2023-04-12
申请号：EP22185964.8
申请日：2022-07-20
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Changbum , KIM, Sunghoon
IPC分类号： H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H01L29/06 , H01L29/08 , G11C16/04 , G11C16/26
摘要： A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction (Z), extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction (Y) and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements (110, 120) adjacent to each other in the second direction (Y) and sharing a common active region (CACT) between a first gate structure (115) of the first element (110) and a second gate structure (125) of the second element (120) in the second direction (Y). Boundaries of the common active region (CACT) include an oblique boundary (DE) extending in an oblique direction forming an angle (θ1) between 0 and 90 degrees with the second direction (Y).

26. 发明公开

EP4426082A1 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开
公开(公告)号：EP4426082A1
公开(公告)日：2024-09-04
申请号：EP24158579.3
申请日：2024-02-20
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Hyunjung , PARK, Sejun , LEE, Jaeduk , JUNG, Eiwhan
IPC分类号： H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC分类号： H10B43/35 , H10B43/27 , H10B41/35 , H10B41/27
摘要： A semiconductor device includes a first semiconductor structure (PERI; S1) including a substrate (201), circuit devices (220) on the substrate (201), and circuit interconnection lines (280) on the circuit devices (220); and a second semiconductor structure (CELL; S2) on the first semiconductor structure (PERI; S1) and having a first region (R1) and a second region (R2), wherein the second semiconductor structure (CELL; S2) includes gate electrodes (130); first channel structures (CH) in the first region (R1); second channel structures (SCH) in the first region (R1); and contact plugs (170) in the second region (R2), the gate electrodes (130) include first gate electrodes (130U2, 130U1, 130M, 130D2, 130L1, 130L2) having a first thickness in the vertical direction (Z) in the first region (R1) and second gate electrodes (130U1_1, 130U1_2, 130U1_3) having a second thickness (T3) in the vertical direction (Z) greater than the first thickness in the first region (R1), and the second gate electrodes (130U1_1, 130U1_2, 130U1_3) are commonly connected to one of the contact plugs (170).

27. 发明公开

EP4412423A1 SEMICONDUCTOR STRUCTURE FOR 3D MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：EP4412423A1
公开(公告)日：2024-08-07
申请号：EP23159589.3
申请日：2023-03-02
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： SHEN, Kuan-Yuan , CHIU, Chia-Jung
IPC分类号： H10B41/27 , H10B41/50 , H10B43/27 , H10B43/50
CPC分类号： H10B43/27 , H10B43/50 , H10B41/50 , H10B41/27
摘要： Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layer separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.

28. 发明公开

EP4383342A2 SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-实审
公开(公告)号：EP4383342A2
公开(公告)日：2024-06-12
申请号：EP23213815.6
申请日：2023-12-01
申请人： Samsung Electronics Co., Ltd.
发明人： YUN, Kangoh , LEE, Sohyun , LEE, Dongjin , LIM, Junhee
IPC分类号： H01L29/08 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40 , H01L21/8234
CPC分类号： H10B43/27 , H10B43/40 , H10B43/10 , H10B41/27 , H10B41/40 , H10B41/10 , H01L29/0847 , H01L21/823418
摘要： A semiconductor device includes a substrate including an active region including a central active region extending in a first direction and first to fourth extended active regions extending from an edge of the central active region in a second direction perpendicular to the first direction, and a device isolation layer defining the active region; and first to fourth gate structures on the active region and spaced apart from one another, wherein the central active region, the first to fourth extended active regions, and the first to fourth gate structures constitute first to fourth pass transistors, the first to fourth pass transistors share one drain region on the central active region, and the active region has an H shape in a plan view.

29. 发明公开

EP4376001A1 NONVOLATILE MEMORY DEVICE 审中-实审
公开(公告)号：EP4376001A1
公开(公告)日：2024-05-29
申请号：EP23191695.8
申请日：2023-08-16
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Youse , KIM, Hyunggon , LIM, Bongsoon
IPC分类号： G11C5/02 , G11C16/04 , G11C16/08 , G11C16/24 , H10B41/27 , H10B41/50 , H10B43/27 , H10B43/50
CPC分类号： G11C16/0483 , G11C16/08 , G11C5/025 , G11C16/24 , H10B43/27 , H10B43/50 , H10B43/10
摘要： A nonvolatile memory device (100) includes a first semiconductor layer (L1) and a second semiconductor layer (L2). The first semiconductor layer (L1) includes word-lines (WL), bit-lines (BL) and a memory cell array (200) which includes one or more memory blocks (BLK) spaced apart from each other, one or more dummy blocks (DBLK) between the one or more memory blocks (BLK) and a through-hole via region (BLTHVR). The second semiconductor layer (L2) is under the first semiconductor layer (L1) includes a control circuit (450). The control circuit (450) divides each of the one or more dummy blocks (DBLK) into an adjacent sub-block (DSBLK11; DSBLK21) directly contacting the through-hole via region and a non-adjacent sub-block (DSBLK12; DSBLK22) based on a relative distance from the through-hole via region (BLTHVR) in the first direction and uses each of the non-adjacent sub-blocks (DSBLK12, DSBLK22) as a sub-block to store data.

30. 发明公开

EP4344383A1 SEMICONDUCTOR MEMORY DEVICE 审中-实审
公开(公告)号：EP4344383A1
公开(公告)日：2024-03-27
申请号：EP23161763.0
申请日：2023-03-14
申请人： Kioxia Corporation
发明人： HASHIMOTO, Toshifumi
IPC分类号： H10B43/50 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B41/50 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B41/41
摘要： A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region (R MH ) to a third memory region (R MH ), a first region (R HU ) between the first memory region and the second memory region, and a second region (R HU ) between the second memory region and the third memory region. The first structure (FS) comprises first via contact electrodes (CC) in the first region. The second structure (FS) comprises second via contact electrodes (CC) in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.

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