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21. 发明公开

EP4273909A2 SEMICONDUCTOR MODULE WITH LIQUID DIELECTRIC ENCAPSULANT 审中-实审
公开(公告)号：EP4273909A2
公开(公告)日：2023-11-08
申请号：EP23170980.9
申请日：2023-05-02
申请人： Infineon Technologies AG
发明人： TROSKA, Georg , HARTUNG, Hans
IPC分类号： H01L21/56 , H01L23/24 , H01L23/31 , H01L21/54 , H01L23/20
摘要： A semiconductor module includes a power electronics carrier including a metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a volume of electrically insulating encapsulant that fills the interior volume and encapsulates the power semiconductor die, and a pressure compensation element disposed on or within the electrically insulating encapsulant, wherein the electrically insulating encapsulant is a liquid, wherein the semiconductor module forms an impermeable seal that contains the volume of electrically insulating encapsulant, and wherein the pressure compensation element is configured to maintain the electrically insulating encapsulant at a substantially constant pressure during thermal expansion and thermal contraction of the electrically insulating encapsulant.

22. 发明公开

EP4213180A3 CHIP-SCALE PACKAGE 审中-实审
公开(公告)号：EP4213180A3
公开(公告)日：2023-11-08
申请号：EP22213451.2
申请日：2022-12-14
申请人： Nexperia B.V.
发明人： Poelma, Regnerus Hermannus , Bünning, Hartmut , Berglund, Stefan , Funke, Hans-Juergen , Kuipers, Johannes Josinus , Stokkermans, Joep , Schnitt, Wolfgang
IPC分类号： H01L21/027 , H01L21/033 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/31 , H01L23/00
摘要： Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device.
According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

23. 发明公开

EP4270476A1 SEMICONDUCTOR PACKAGE AND METHOD FOR MARKING A SEMICONDUCTOR PACKAGE 审中-实审
公开(公告)号：EP4270476A1
公开(公告)日：2023-11-01
申请号：EP22170987.6
申请日：2022-04-29
申请人： Infineon Technologies Austria AG
发明人： LOW, Hwee Yin , ABDUL RANI, Badrus Hisham , LIM, Wee Aun Jason , WAHID, Muhamad Hairul Fauzi , LOH, Ai Yun
IPC分类号： H01L23/544 , H01L23/36 , H01L21/56 , H01L23/31 , H01L21/683
摘要： In an embodiment, a semiconductor package 10, 100 is provided that comprises a first package surface 11 and a second package surface 12 opposing the first surface 11, a plastic molding 13 and one or more semiconductor dies 14. The first package surface 11 comprises a first surface 15 of the plastic molding 13 and a first metallic area 16 exposed from the plastic molding 13. The first metallic area 16 comprises a first product marking 17 comprising at least one alphanumeric character and the first surface 15 of the plastic molding 13 comprises a second product marking 18 comprising at least one alphanumeric character.

24. 发明公开

EP4261872A1 MOLDED ELECTRONIC PACKAGE WITH AN ELECTRONIC COMPONENT ENCAPSULATED BETWEEN TWO SUBSTRATES WITH A SPRING MEMBER BETWEEN THE ELECTRONIC COMPONENT AND ONE OF THE SUBSTRATES AND METHOD FOR MANUFACTURING THE SAME 审中-实审
公开(公告)号：EP4261872A1
公开(公告)日：2023-10-18
申请号：EP22167530.9
申请日：2022-04-11
申请人： Nexperia B.V.
发明人： Cheam, Hing Suan , Tan, Wei Leong , Chang, Ting Wei
IPC分类号： H01L21/603 , H01L23/48 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/367 , H01L23/498
摘要： A molded electronic package (1a, 1b) comprises a first substrate (2), a second substrate (3), an electronic component (4) arranged on the first substrate (2), a spring member (5) arranged between the second substrate (3) and the electronic component (4), the spring member (5) comprising a first contact portion (5a) being fixed relative to the second substrate (3) and a second contact portion (5b) physically contacting the electronic component (4), and a body of solidified molding compound (6) encapsulating the electronic component (4) and the spring member (5) and mutually fixing the first substrate (2), the second substrate (3), the electronic component (4) and the spring member (5). The spring member (5) may be fixed to the second substrate (3) by an adhesive layer (e.g., solder). Alternatively or in addition, the spring member (5) may be fixed to the second substrate (3) by a recess in the second substrate (3) in which the first contact portion (5a) is arranged, the recess being configured to mechanically lock a position of the spring member (5) in a direction parallel to the second substrate (3); and/or the spring member (5) may be fixed to the second substrate (3) by one or more protrusions extending from the second substrate (3) and surrounding the first contact portion (5a), the one or more protrusions being configured to mechanically lock a position of the spring member (5) in a direction parallel to the second substrate (3). The second substrate (3) and the spring member (5) may be thermally conductive, wherein at least a portion of a surface of the second substrate (3) is exposed to an outside of the molded electronic package (1a, 1b), the second substrate (3) forming a heatsink for the electronic component (4). The second substrate (3) and the spring member (5) may be electrically conductive, wherein the second substrate (3) comprises: a planar portion (3a), the spring member (5) being arranged in between the planar portion (3a) and the electronic component (4); and a first lead (3b) integrally connected to the planar portion (3a) and extending from said planar portion (3a) and out of the body of solidified molding compound (6), wherein the first lead (3b) is electrically connected to a terminal of the electronic component (4) via the planar portion (3a) and the spring member (5), and forms a package contact of the molded electronic package (1a). Alternatively, the second substrate may comprise a printed circuit board, PCB, comprising a dielectric layer and a circuit arranged on the dielectric layer, wherein the circuit is electrically connected to the electronic component (4) through the spring member (5). The first substrate (2) may be electrically conductive and electrically connected to a terminal of the electronic component (4), wherein the first substrate (2) comprises a pad portion (2a) on which the electronic component (4) is arranged, and wherein the pad portion (2a) comprises a surface that is exposed to an outside of the molded electronic package (6), said surface forming a package contact of the molded electronic package (6), and/or wherein the first substrate (2) further comprises a second lead (2b) integrally formed with the pad portion (2a), said second lead (2b) extending from said pad portion (2a) and out of the body of solidified molding compound (6), wherein the second lead (2b) forms a package contact of the molded electronic package (1a); and/or wherein the electronic component (4) comprises a semiconductor die having a circuit integrated thereon, wherein the circuit comprises a plurality of terminals corresponding to terminals of the electronic component (4), wherein the first substrate (2) preferably comprises a die pad. The molded electronic package (1b) may further comprise: a further package contact (9), a first end thereof being external to the body of solidified molding compound (6), and a second end thereof being encapsulated by the body of solidified molding compound (6); a further spring member comprising a first further contact portion (8a) contacting the second substrate (3), and a second further contact portion (8b) contacting the further package contact (9), wherein the further spring member is electrically conductive, wherein the further spring member is preferably integrally connected to the spring member (5). In a method for manufacturing the molded electronic package (1a, 1b), a molding compound is applied and allowed to solidify to thereby form the body of solidified molding compound (6) upon applying a force (P1, P2, P3) to the second substrate (3), said force (P1, P2, P3) allowing the second contact portion (5b) of the spring member (5) to deform and press against the electronic component (4). At least part of a surface of the second substrate (3) may be kept clear of molding compound, wherein the force (P1) is applied to said part of the surface of the second substrate (3); and/or a first end portion and an opposing second end portion of the second substrate (3) are kept clear of molding compound, wherein the force (P2, P3) is applied to said first end portion and second end portion.

25. 发明公开

EP4258341A2 SEALED CAVITY EMBEDDED IN A SEMICONDUCTOR WAFER 审中-实审
公开(公告)号：EP4258341A2
公开(公告)日：2023-10-11
申请号：EP23161872.9
申请日：2023-03-14
申请人： Analog Devices, Inc.
发明人： JIANG, Yingqi , FIORENZA, James G.
IPC分类号： H01L23/31 , H01L21/56 , H01L23/29 , H01L23/482 , H01L29/20 , H01L29/778
摘要： Techniques are described for forming a sealed cavity within a semiconductor wafer, where a conductor wafer includes a structure, such as a T-gate electrode or passive component, formed over a substrate. The sealed-cavity structure may be embedded into the wafer without interfering with any subsequent processes. That is, once the cavity is closed, any subsequent backend processes may continue as usual.

26. 发明公开

EP4167279A3 POWER SEMICONDUCTOR DEVICE MODULE 审中-实审
公开(公告)号：EP4167279A3
公开(公告)日：2023-09-13
申请号：EP22212270.7
申请日：2013-09-13
申请人： Rohm Co., Ltd.
发明人： HANADA, Toshio
IPC分类号： H01L25/07 , H01L23/28 , H01L25/18 , H02M7/48 , H01L21/56 , H01L23/498 , H01L25/11 , H02M7/00 , H01L23/373
摘要： The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate. There is provided a power module semiconductor device having a vertical terminal transfermold in which structure thereof is simple and the number of parts is reduced, thereby achieving space saving.

27. 发明授权

EP3783645B1 PIN, PIN COMBINATION STRUCTURE, PACKAGING BODY AND MANUFACTURING METHOD THEREFOR 有权
公开(公告)号：EP3783645B1
公开(公告)日：2023-07-12
申请号：EP19886596.6
申请日：2019-05-14
发明人： WU, Hong , LV, Zhen
IPC分类号： H01L23/498 , H01L21/56

28. 发明授权

EP3916933B1 SEMICONDUCTOR SIDE EMITTING LASER LEADFRAME PACKAGE AND METHOD OF PRODUCING SAME 有权
公开(公告)号：EP3916933B1
公开(公告)日：2023-07-05
申请号：EP21174991.6
申请日：2021-05-20
发明人： JU, JinHan , CHARLEBOIS, Gabriel
IPC分类号： H01S5/02234 , H01S5/0232 , H01L23/00 , H01L33/48 , H01L21/56 , H01L23/31 , H01L23/482 , H01L23/495 , H01S5/026 , H01S5/40

29. 发明公开

EP4191663A1 METHOD OF MANUFACTURING A SIC-BASED ELECTRONIC DEVICE WITH A PASSIVATION LAYER AND AN ANCHORING ELEMENT AND AN ELECTRONIC DEVICE MANUFACTURED THEREBY 审中-实审
公开(公告)号：EP4191663A1
公开(公告)日：2023-06-07
申请号：EP22207266.2
申请日：2022-11-14
申请人： STMicroelectronics S.r.l.
发明人： PUGLISI, Valeria , BELLOCCHI, Gabriele , RASCUNA', Simone
IPC分类号： H01L23/31 , H01L21/56 , H01L29/16
摘要： An electronic device (50; 100), comprising: a semiconductor body (53) of silicon carbide; an insulating layer (61; 102) on a surface (53a) of the semiconductor body (53); a layer of metal material (58) extending in part on the surface (53a) of the semiconductor body (53) and in part on the insulating layer (61); a SiN interface layer on the layer of metal material and the insulating layer; a passivation layer (69) on the interface layer; and an anchoring element (82) that protrudes from the passivation layer (69) towards the first insulating layer (61; 102) and extends in the first insulating layer (61; 102) underneath the interface layer.

30. 发明公开

EP4191662A1 ENCAPSULATION MODULE AND ELECTRONIC DEVICE 审中-实审
公开(公告)号：EP4191662A1
公开(公告)日：2023-06-07
申请号：EP21860419.7
申请日：2021-08-25
申请人： Huawei Technologies Co., Ltd.
发明人： LV, Yatao , TANG, Qingguo , WANG, Ning
IPC分类号： H01L23/31 , H01L21/56
摘要： Embodiments of this application disclose a packaging module and an electronic device. Both a first surface and a second surface of a PCB in the packaging module are covered with a molding layer, a conductive pin is electrically connected to the PCB, the conductive pin is packaged inside the molding layer along a stacking direction of the PCB and the molding layer, and the conductive pin is partially exposed on an outer surface of the molding layer. When the packaging module performs electrical interaction with another element, the PCB outputs or inputs an electrical signal by using the conductive pin. In this way, there is no need to reserve a through hole on a packaging side of the packaging module, the packaging module may be arranged at a position close to a chip, and there are short wires between the packaging module and the chip. This reduces a size of an electronic device and reduces a power distribution loss of the electronic device.

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