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21. 发明公开

EP4276912A1 A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4276912A1
公开(公告)日：2023-11-15
申请号：EP22172478.4
申请日：2022-05-10
申请人： Nexperia B.V.
发明人： Peake, Steven , Siddiqui, MD Imran
IPC分类号： H01L29/40 , H01L21/336 , H01L29/78 , H01L21/66
摘要： A method of creating a vertical semiconductor device, the method comprising the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material such that oxide material is formed inside the vertical trench, wherein ledges are formed by said oxide material, inside said vertical trench, as a result of said LOCOS process, so that a lower region of reduced lateral distance is formed between said oxide material, at a base of said trench, depositing said trench with polysilicon and etching said polysilicon downward up to the oxide material using interferometric end point detection, such that polysilicon remains in said lower region.

22. 发明公开

EP4270490A1 MOSFET DEVICE AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4270490A1
公开(公告)日：2023-11-01
申请号：EP23741247.3
申请日：2023-03-20
申请人： Yuezhou Semiconductor Manufacturing Electronics (Shaoxing) Corp
发明人： LI, Xiang , XIE, Zhiping , CONG, Maojie , LIANG, Xinying , ZHANG, Yukai
IPC分类号： H01L29/78 , H04L69/32 , H04L67/00 , H01L21/77 , H01L21/223 , H01L21/336
摘要： The present invention provides a metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. First, a first implantation region easy to diffuse is formed, and then, a second implantation region which is not easy to diffuse and has a deeper junction is formed in sequence. After ion implantation in a source region and the like is completed, the first implantation region is activated to form a required well region in a mode of junction diffusion in the first implantation region, and the second implantation region is used for increasing the depth of the well region, thereby avoiding the problems of damage to the surface of a substrate at a channel and roughness of the surface of the channel of the device caused by the formation of a P well directly through multiple Al ion implantation in the prior art, and achieving high conductivity of the device. In addition, the ion implantation in the first implantation region, the second implantation region and the source region can use a same mask layer, so that the process is simple to implement, and the photoetching frequency can be effectively reduced.

23. 发明公开

EP4270487A1 POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING A TRANSISTOR DEVICE 审中-公开
公开(公告)号：EP4270487A1
公开(公告)日：2023-11-01
申请号：EP22170661.7
申请日：2022-04-28
申请人： Infineon Technologies Austria AG
发明人： TEGEN, Stefan , HENSON, Timothy
IPC分类号： H01L29/40 , H01L29/78 , H01L21/336
摘要： In an embodiment, a power transistor device 10, 40, 50, 60 comprises a substrate 11 formed of crystalline silicon and having a first surface 12 and a second surface 13 opposing the first surface 12, a field plate 14 formed of polysilicon that is electrically connected with the substrate 11 and an interfacial silicon nitride layer 15 that is arranged between the polysilicon of the field plate 14 and the crystalline silicon of the substrate 11.

24. 发明公开

EP4266354A1 SIC SEMICONDUCTOR ELEMENT MANUFACTURING METHOD AND SICMOSFET 审中-实审
公开(公告)号：EP4266354A1
公开(公告)日：2023-10-25
申请号：EP21906152.0
申请日：2021-10-22
申请人： Kyoto University
发明人： KIMOTO, Tsunenobu , TACHIKI, Keita
IPC分类号： H01L21/336 , H01L21/31 , H01L21/316 , H01L29/78
摘要： A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H 2 gas under Si-excess atmosphere within a temperature range of 1000°C to 1350°C, a step of depositing, by a CVD method, a SiO 2 film 2 on the SiC substrate 1 at such a temperature that the SiC substrate 1 is not oxidized, and a step of thermally treating the SiC substrate 1, on which the SiO 2 film 2 is deposited, in NO gas atmosphere within a temperature range of 1150°C to 1350°C.

25. 发明公开

EP4261894A1 TRENCH-GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-实审
公开(公告)号：EP4261894A1
公开(公告)日：2023-10-18
申请号：EP22168316.2
申请日：2022-04-14
申请人： Nexperia B.V.
发明人： Siddiqui, Imran , Peake, Steven
IPC分类号： H01L29/78 , H01L21/336 , H01L29/40
摘要： The present disclosure relates to a trench-gate semiconductor device and a manufacturing method therefor. The device comprises one or more unit cells, and each unit cell comprises a trench a first oxide layer arranged on an upper portion of a side wall of the trench, said first oxide layer forming a gate oxide of the unit cell, and a second oxide layer arranged on a lower portion of the side wall and on a bottom of the trench. Furthermore, each unit cell comprises a gate arranged inside the trench, separated from the upper portion of the side wall by the first oxide layer, said first polysilicon region forming a gate of the unit cell, a second polysilicon region arranged inside the trench, separated from the lower portion of the side wall and from the bottom of the trench by the second oxide layer, said second polysilicon region forming a buried source of the unit cell, and a third oxide layer arranged in between the first polysilicon region and the second polysilicon region. Furthermore, each unit cell comprises a body region of a first charge type, wherein the body region is separated from the gate by the first oxide layer. A first distance from a top surface of the semiconductor region to a bottom surface of the body region is equal to or less than 3 micron, and a second distance from said top surface of the semiconductor region to a bottom surface of the first polysilicon region extends at least 0.3 micron beyond said bottom surface of the body region.

26. 发明公开

EP4258363A1 SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME 审中-实审
公开(公告)号：EP4258363A1
公开(公告)日：2023-10-11
申请号：EP20963817.0
申请日：2020-12-01
申请人： NISSAN MOTOR CO., LTD. , RENAULT S.A.S.
发明人： NI, Wei , HAYASHI, Tetsuya , NUMAKURA, Keiichiro , MARUI, Toshiharu , TANAKA, Ryouta , IWASAKI, Yuichi
IPC分类号： H01L29/78 , H01L21/336
摘要： A semiconductor device includes: a drift region that is arranged on a main surface of a substrate, and has a higher impurity concentration than the substrate; a first well region that is connected to the drift region; and a second well region that is arranged adjacent to the first well region and faces the drift region. The second well region has a higher impurity concentration than the first well region. A distance between the source region that faces the drift region via the first well region and the drift region is greater than a distance between the second well region and the drift region, in a direction parallel to the main surface of the substrate. A depletion layer extending from the second well region reaches the drift region.

27. 发明公开

EP4254508A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4254508A1
公开(公告)日：2023-10-04
申请号：EP21896387.4
申请日：2021-07-30
申请人： Gree Electric Appliances, Inc. of Zhuhai
发明人： LIN, Yiren , SHI, Bo , CHEN, Daokun , ZENG, Dan
IPC分类号： H01L29/78 , H01L21/336
摘要： The disclosure relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method therefor. The semiconductor device includes a semiconductor substrate, an epitaxial layer grown on a side of the semiconductor substrate; a quantum dot transport layer formed on the epitaxial layer; and a gate oxide layer formed on the quantum dot transport layer. With this arrangement, the semiconductor device provided by the present disclosure may reduce a threshold voltage while ensuring gate electrode reliability.

28. 发明公开

EP4254480A1 INTEGRATED CIRCUIT STRUCTURES WITH FULL-WRAP CONTACT STRUCTURE 审中-实审
公开(公告)号：EP4254480A1
公开(公告)日：2023-10-04
申请号：EP23156297.6
申请日：2023-02-13
申请人： INTEL Corporation
发明人： GULER, Leonard P. , WALLACE, Charles H. , GHANI, Tahir
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/336 , H01L29/775 , H01L29/06 , H01L29/417 , H01L29/423 , B82Y10/00 , H01L29/08
摘要： Integrated circuit structures having full-wrap contact structures, and methods of fabricating integrated circuit structures having full-wrap contact structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. The conductive trench contact structure is electrically connected to a top of the epitaxial source or drain structure and to at least 10% of a length of each side of the epitaxial source or drain structure.

30. 发明授权

EP3611765B1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH LATCHUP IMMUNITY 有权
公开(公告)号：EP3611765B1
公开(公告)日：2023-09-20
申请号：EP19188936.9
申请日：2019-07-29
发明人： Nguyen, Chi Dong , Rupp, Andreas
IPC分类号： H01L21/336 , H01L29/78 , H01L29/08 , H01L29/10

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