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21. 发明公开

EP0446891A2 Laser beam controller 失效
标题翻译： Laserstrahlregeleinrichtung。
公开(公告)号：EP0446891A2
公开(公告)日：1991-09-18
申请号：EP91103831.3
申请日：1991-03-13
申请人： MITA INDUSTRIAL CO. LTD.
发明人： Yamamoto, Haruo , Shimatani, Akira , Kumamoto, Hidechika , Fujimoto, Masaya , Matsushita, Tsukasa
IPC分类号： H04N1/40 , H03K5/13 , H03K7/08 , G06K15/12
CPC分类号： H03K5/131 , G06K15/1209 , H03K7/08 , H03K2005/00234 , H04N1/4056
摘要： A laser beam controller comprises a basic pulse signal generating circuit (1), a delay circuit (26a-e), a delay control circuit (23-25,27-36), a pulse generating circuit (37-49) and a laser beam generator (18). The basic pulse signal generating circuit (1) generates periodically occurring basic pulse signal. The delay circuit (26a-e) delays the basic pulse signal. The delay control circuit (23-25,27-36) controls the delay time of the basic pulse in the delay circuit (26a-e) according to image data. The pulse generating circuit (37-49) generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator (18) generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit (37-49).
According to the controller, any desired gradation of a pixel of the image is desirably produced.
摘要翻译：激光束控制器包括基本脉冲信号发生电路（1），延迟电路（26a-e），延迟控制电路（23-25,27-36），脉冲发生电路（37-49）和激光器光束发生器（18）。基本脉冲信号发生电路（1）产生周期性发生的基本脉冲信号。延迟电路（26a-e）延迟基本脉冲信号。延迟控制电路（23-25,27-36）根据图像数据控制延迟电路（26a-e）中的基本脉冲的延迟时间。脉冲发生电路（37-49）产生具有与基本脉冲信号的延迟时间对应的宽度的输出脉冲。激光束发生器（18）通过所述脉冲发生电路（37-49）产生与输出脉冲的宽度相对应的持续时间的激光束。根据控制器，期望产生图像的像素的任何期望的灰度。

22. 发明公开

EP0183875A3 Clocked logic device 失效
标题翻译：时钟逻辑器件
公开(公告)号：EP0183875A3
公开(公告)日：1987-05-27
申请号：EP84115999
申请日：1984-12-20
申请人： ADVANTEST CORPORATION
发明人： Misono, Toshiaki
IPC分类号： H03K05/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00234 , H04L7/0338
摘要： A clocked logic circuit (24) operates in synchronism with a clock and is supplied with an input binary signal asynchronous with the clock for issuing an output binary signal. A phase detector circuit (25) produces a phase difference signal indicating which of k divided phase regions of one period of the clock, the phase difference between the input binary signal and the clock falls in. The phase difference signal is delayed by a matching delay means (31) for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.

23. 发明公开

EP0119616A3 PROGRAMMABLE DELAY CIRCUIT 失效
标题翻译：可编程延时电路
公开(公告)号：EP0119616A3
公开(公告)日：1986-12-30
申请号：EP84102947
申请日：1984-03-16
申请人： TEKTRONIX, INC.
发明人： JACKSON, RONALD MARK
IPC分类号： H03K3/03 , H03K5/00 , H03K5/13 , H03K5/14
CPC分类号： H03K3/0315 , H03K5/131 , H03K2005/00097 , H03K2005/00234 , Y10S331/03
摘要： A programmable delay circuit comprises input and out put multiplexers, a delay device provided between the mul tiplexers, and a negative feedback path. When the input multiplexer selects an input logic signal, the delay time is controlled by the output multiplexer. When the input multi plexer selects the feedback path, the delay circuit acts as a ring oscillator for generating a square-wave signal whose period is twice the selected delay time. Additional delay de vices and multiplexers may be provided between the input and output multiplexers.

24. 发明公开

EP0183875A2 Clocked logic device 失效
标题翻译：时钟逻辑电路。
公开(公告)号：EP0183875A2
公开(公告)日：1986-06-11
申请号：EP84115999.9
申请日：1984-12-20
申请人： ADVANTEST CORPORATION
发明人： Misono, Toshiaki
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00234 , H04L7/0338
摘要： A clocked logic circuit (24) operates in synchronism with a clock and is supplied with an input binary signal asynchronous with the clock for issuing an output binary signal. A phase detector circuit (25) produces a phase difference signal indicating which of k divided phase regions of one period of the clock, the phase difference between the input binary signal and the clock falls in. The phase difference signal is delayed by a matching delay means (31) for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.

25. 发明公开

EP2160835A1 METHOD AND APPARATUS FOR PROGRAMMABLE DELAY HAVING FINE DELAY RESOLUTION 审中-公开
标题翻译：方法和装置用细延迟分辨率的可编程延迟
公开(公告)号：EP2160835A1
公开(公告)日：2010-03-10
申请号：EP08769537.5
申请日：2008-05-20
申请人： QUALCOMM Incorporated
发明人： GONZALEZ, Jason , DANG, Harry H. , DANG, Vannam
IPC分类号： H03K5/00
CPC分类号： H03K5/131 , H03K2005/00058 , H03K2005/00234
摘要： An programmable delay apparatus (200) includes a first delay stage (210) having a delay cell (230) which includes a passive network (214), where the first stage is capable of providing a first time delay. The apparatus further includes a second delay stage (220) which includes a plurality of delay cells (240_l, 240_2, 240_3, 240_4, 240_5, 240_6), where each delay cell is capable of providing a second time delay which is larger than the first time delay. A method for delaying an input signal (INPUT) includes receiving a delay select command (sel_dly0... sel_dly6) based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells (210, 220) according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element (230) which comprises a passive network (214).

26. 发明授权

EP0878908B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译：具有用于检测所述输入信号状态的互补时钟和电路的半导体装置
公开(公告)号：EP0878908B1
公开(公告)日：2001-12-05
申请号：EP97307632.6
申请日：1997-09-29
申请人： FUJITSU LIMITED
发明人： Taguchi, Masao , Tomita, Hiroyoshi , Matsuzaki, Yasurou
IPC分类号： H03K5/151 , G11C7/00
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814

27. 发明公开

EP1148645A2 Phase shift circuit and fm detector circuit 审中-公开
标题翻译： Phasenverschiebungsschaltung和FM Detektorschaltung
公开(公告)号：EP1148645A2
公开(公告)日：2001-10-24
申请号：EP01303006.9
申请日：2001-03-29
申请人： SANYO ELECTRIC CO., LTD.
发明人： Saeki, Takao , Iijima, Takashi , Yamamoto, Hiroya , Suzuki, Jun , Kinoshita, Masaki
IPC分类号： H03K5/13 , H03K9/06
CPC分类号： H03K9/06 , H03D3/04 , H03K5/13 , H03K2005/00078 , H03K2005/00156 , H03K2005/00234
摘要： Transistors (12a, 12b) turn on and off with mutually opposite phase input signals. Capacitors (16a, 16b) discharge when the transistors (12a, 12b) turn on, and capacitors (16a, 16b) are charged by constant current from constant current sources (18a, 18b) when the transistors (12a, 12b) turn off. As a result, a gradually rising voltage is obtained at the positive input ends of comparators (14a, 14b) while the input signals are L. By comparing this with fixed voltages of reference sources (20a, 20b), signals having rise timing shifted from input signals by 90° are obtained. The outputs of the comparators (14a, 14b) are mutually shifted by 180°, and at the rise of these outputs, an RS flip-flop (22) is set and reset so that signals delayed in phase by 90° with respect to the input signals are obtained at its outputs.
摘要翻译：晶体管（12a，12b）通过相互相反的相位输入信号导通和截止。当晶体管（12a，12b）关闭时，晶体管（12a，12b）导通时，电容器（16a，16b）放电，并且电容器（16a，16b）由来自恒定电流源（18a，18b）的恒定电流充电。结果，当输入信号为L时，在比较器（14a，14b）的正输入端处获得逐渐上升的电压。通过与参考源（20a，20b）的固定电压进行比较，具有上升定时的信号从输入信号为90°。比较器（14a，14b）的输出相互偏移180°，在这些输出端上升时，RS触发器（22）被置位和复位，使相位延迟90°的信号相对于在其输出端获得输入信号。

28. 发明公开

EP0878908A3 Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译： Halbleitervorrichtung mitkomplementäremTakt und Schaltung zur Detektion des Eingangssignalzustandesdafür
公开(公告)号：EP0878908A3
公开(公告)日：1999-01-20
申请号：EP97307632.6
申请日：1997-09-29
申请人： FUJITSU LIMITED
发明人： Taguchi, Masao , Tomita, Hiroyoshi , Matsuzaki, Yasurou
IPC分类号： H03K5/151 , G11C7/00
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) (11) is supplied with a first eternal clock (CLK) and outputs a first internal clock (CLK1). A second clock input circuit (buffer) (12) is supplied with a second external clock (/CLK) complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit (22) generates a 1/2 phase shift signal 180° out of phase with the first internal clock (CLK). A second external clock state detection circuit judges whether the second external clock (/CLK) is input to the second clock input buffer. A switch (23) is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
摘要翻译：公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的类型的系统和内部产生180°相位时钟的系统的系统。第一时钟输入电路（缓冲器）（11）被提供有第一永久时钟（CLK）并输出第一内部时钟（CLK1）。第二时钟输入电路（缓冲器）（12）被提供有与第一外部时钟互补的第二外部时钟（/ CLK）并输出第二时钟。 1/2相位时钟发生电路（22）产生与第一内部时钟（CLK）180°异相的1/2相移信号。第二外部时钟状态检测电路判断第二外部时钟（/ CLK）是否输入到第二时钟输入缓冲器。当输入第二外部时钟时，开关（23）被操作以产生第二时钟作为第二内部时钟，并且当不输入第二外部时钟时产生1/2相移信号作为第二内部时钟在第二外部时钟状态检测电路上判断。

29. 发明公开

EP0878908A2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译：具有用于检测所述输入信号状态的互补时钟和电路的半导体装置
公开(公告)号：EP0878908A2
公开(公告)日：1998-11-18
申请号：EP97307632.6
申请日：1997-09-29
申请人： FUJITSU LIMITED
发明人： Taguchi, Masao , Tomita, Hiroyoshi , Matsuzaki, Yasurou
IPC分类号： H03K5/151 , G11C7/00
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) (11) is supplied with a first eternal clock (CLK) and outputs a first internal clock (CLK1). A second clock input circuit (buffer) (12) is supplied with a second external clock (/CLK) complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit (22) generates a 1/2 phase shift signal 180° out of phase with the first internal clock (CLK). A second external clock state detection circuit judges whether the second external clock (/CLK) is input to the second clock input buffer. A switch (23) is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

30. 发明授权

EP0355329B1 Schaltungsanordnung zur Phasenverschiebung 失效
标题翻译：相位转换电路
公开(公告)号：EP0355329B1
公开(公告)日：1992-09-02
申请号：EP89111948.9
申请日：1989-06-30
申请人： ANT Nachrichtentechnik GmbH
发明人： Sperlich, Josef, Dipl.-Ing. , Thier, Heinz, Dipl.-Ing.
IPC分类号： H03H11/20 , H03K5/13
CPC分类号： H03H11/20 , H03K2005/00052 , H03K2005/00234 , H03K2005/00286

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