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21. 发明公开

EP1068565A2 ACCELERATION AND SECURITY ENHANCEMENTS FOR ELLIPTIC CURVE AND RSA COPROCESSORS 有权
标题翻译：加速和安全改进椭圆曲线的协处理器计算与RSA函数
公开(公告)号：EP1068565A2
公开(公告)日：2001-01-17
申请号：EP00900113.2
申请日：2000-01-07
申请人： Fortress U & T Ltd.
发明人： GRESSEL, Carmi, David , HADAD, Isaac , DROR, Itai , MOLCHANOV, Alexey , MOSTOVOY, Michael
IPC分类号： G06F1/00
CPC分类号： G06F21/72 , G06F7/588 , G06F7/72 , G06F7/723 , G06F7/725 , G06F7/728 , G06F2207/7261 , H04L9/12 , H04L9/3066 , H04L2209/04 , H04L2209/08 , H04L2209/125
摘要： This invention discloses apparatus and methods for accelerating processing, loading (10) and unloading (30) of data from and to a plurality of memory addresses in a CPU (1300) having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.

22. 发明公开

EP1038371A1 TRANSFORMATION METHODS FOR OPTIMIZING ELLIPTIC CURVE CRYPTOGRAPHIC COMPUTATIONS 审中-公开
标题翻译： UNWANDLUNGSVERFAHREN以优化椭圆曲线的加密计算
公开(公告)号：EP1038371A1
公开(公告)日：2000-09-27
申请号：EP98965973.5
申请日：1998-12-04
申请人： Secured Information Technology, Inc. , STATE OF OREGON BY AND THROUGH THE OREGON STATE BOARD OF HIGHER EDUCATION ON BEHALF OF OREGON STATE UNIVERSITY
发明人： KOC, Cetin, Kaya , BEAHAN, John, J., Jr. , SADEGHI, Behzad
IPC分类号： H04L9/30
CPC分类号： G06F7/724 , G06F7/725 , G06F7/728 , H04L9/3073
摘要： The present invention provides a transformation method for obtaining optimized hardware and software implementations of elliptic curve cryptographic systems, including elliptic curve encryption, decryption, and signature functions. The method is applicable to any elliptic curve group G defined over any field F. More specifically, the present invention is characterized by speeding up the elliptic curve point multiplication operation, which consists of the calculation Q = eP, where P is a member of G and e is an integer. This is achieved by transforming P = (x, y) to a point P' = (x', y') in order to compute Q' = (u, v = eP'). The point P' is not necessarily on the elliptic curve, but by performing calculation on P' and transforming the resulting Q' back into G, it may be possible to calculate Q more efficiently than utilizing a direct method. The present invention also includes a method for optimizing the calculation of cryptographic operations involving arbitrary expressions in finite field arithmetic through a transformation method that permits the use of any field F in an efficient manner. The invention includes a method for optimizing arbitrary finite calculation in any finite field. The present invention teaches a set of transformations of cryptographic calculations that allows the use of other known techniques that have only been applicable to certain limited special cases prior to this invention.

23. 发明公开

EP0917047A3 Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method 有权
标题翻译：方法和装置的模逆用于与程序用于执行该方法的固定信息和存储介质
公开(公告)号：EP0917047A3
公开(公告)日：2000-07-26
申请号：EP98120939.8
申请日：1998-11-04
申请人： Nippon Telegraph and Telephone Corporation
发明人： Kobayashi, Tetsutaro Nippon Telegraph & Telephone , Morita, Hikaru Nippon Telegraph & Telephone Corp.
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： Values X and N of n bits and a parameter t are input, thenY=X2-t mod N is calculated, then an extended binary GCD algorism is executed for Y to obtain S=Y-12k mod N and k, and R=S2-(k+t-2n) is calculated for S, thereby obtaining a Montgomery inverse R=X-122n mod N of X on a residue class ring Z/NZ.

24. 发明公开

EP1012703A1 COPROCESSEUR D'ARITHMETIQUE MODULAIRE COMPORTANT UN CIRCUIT DE DIVISION ENTIERE 失效
标题翻译：协处理器整数分频电路MODULA算术
公开(公告)号：EP1012703A1
公开(公告)日：2000-06-28
申请号：EP97900619.4
申请日：1997-01-09
申请人： STMicroelectronics S.A.
发明人： MONIER, Guy"La Pinsonnette"
IPC分类号： G06F7/72 , G06F7/52
CPC分类号： G06F7/728 , G06F7/535 , G06F2207/5353
摘要： A modular arithmetic coprocessor for performing calculations according to the Montgomery method, and comprising a division circuit for performing integer divisions. The integer division circuit calculates the division of binary data A coded over n' + n' bits by binary data B coded over n bits, with A, B, n, n' and n' being integers other than zero. For this functionality, the division circuit comprises first and second n-bit registers for containing binary data A and the division result, a third n-bit register for containing an intermediate result, a fourth n-bit register for containing binary data B, two subtracting circuits each having first and second serial inputs and a serial output, and a test circuit having an input and an output.

25. 发明公开

EP1008026A4 IMPROVED APPARATUS & METHOD FOR MODULAR MULTIPLICATION & EXPONENTIATION BASED ON MONTGOMERY MULTIPLICATION 失效
标题翻译：基于MONTGOMERYMULTIPLIKATION FOR模乘幂改进的装置和方法
公开(公告)号：EP1008026A4
公开(公告)日：2000-06-14
申请号：EP98910967
申请日：1998-03-29
申请人： FORTRESS U & T LTD
发明人： HADAD ISAAC , ARAZI BENJAMIN , GRESSEL CARMI DAVID , DROR ITAI
IPC分类号： G06F7/52 , G06F7/72 , G09C1/00 , G06F1/02 , G06F7/544
CPC分类号： G06F7/728
摘要： This invention discloses a modular multiplication and exponentiation method and system including a serial-parallel arithmetic logic unit (ALU) including a single modular multiplying device (4 OPERAND MODULAR MULTIPLIER) having a single carry-save adder (410).
摘要翻译：模算术方法和微电子装置。因此，用于执行交错蒙哥马利型乘法和平方运算的序列，涉及执行仅使用单个进位保存加法器模乘和squarings的序列。每个乘法操作用于执行使用预期设备的确定性矿的值Y0三个自然整数乘法运算相当于，求其结果也被求幂。

26. 发明授权

EP0778518B1 Procédé de production d'un paramètre J0 associé à la mise en oeuvre d'opérations modulaires selon la méthode de Montgomery 失效转让
标题翻译：上根据蒙哥马利方法使用模运算来生成参数J0的方法
公开(公告)号：EP0778518B1
公开(公告)日：2000-01-19
申请号：EP96470022.3
申请日：1996-11-27
申请人： STMicroelectronics S.A.
发明人： Monier, Guy
IPC分类号： G06F7/72
CPC分类号： G06F7/728

27. 发明公开

EP0917047A2 Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method 有权
标题翻译： Gerätfürdie modulare Inversion zur Sicherung von信息
公开(公告)号：EP0917047A2
公开(公告)日：1999-05-19
申请号：EP98120939.8
申请日：1998-11-04
申请人： Nippon Telegraph and Telephone Corporation
发明人： Kobayashi, Tetsutaro Nippon Telegraph & Telephone , Morita, Hikaru Nippon Telegraph & Telephone Corp.
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： Values X and N of n bits and a parameter t are input, then Y=X2 -t mod N is calculated, then an extended binary GCD algorism is executed for Y to obtain S=Y -1 2 k mod N and k, and R=S2 -(k+t-2n) is calculated for S, thereby obtaining a Montgomery inverse R=X -1 2 2n mod N of X on a residue class ring Z/NZ.
摘要翻译：输入n位和参数t的值X和N，然后计算Y = X2 <-t> mod N，然后对Y执行扩展二进制GCD算法以获得S = Y <2> 对于S，计算出S N和K，并且R = S2 < - （k + t-2n）>，从而获得残留类别Z上的X的蒙哥马利反R = X -1 -2 2n mod /新西兰。

28. 发明公开

EP0890147A1 CO-PROCESSOR FOR PERFORMING MODULAR MULTIPLICATION 失效
标题翻译：协处理器模乘上运行
公开(公告)号：EP0890147A1
公开(公告)日：1999-01-13
申请号：EP97950044.0
申请日：1997-10-22
申请人： Motorola Limited
发明人： HOBSON, Russell , McGINN, Peter
IPC分类号： G06F7 , G09C1
CPC分类号： G06F7/722 , G06F7/723 , G06F7/728
摘要： A co-processor (Fig. 2) for performing modular multiplication comprising: means for receiving B and N binary data streams (bstr, nstr); means for receiving a data value A; adder means (Add1, Add2), subtractor means (Sub1, Sub2, Sub3) and multiplier means (Mul1, Mul2) coupled to sequentially process the B and N binary data streams and the data value A to produce a modulo-reduced multiplication value (A*B) mod N; wherein the means for receiving the binary data streams comprises: random access memory (B-RAM, S-RAM) for holding B and N values; and parallel-serial interface means for receiving parallel data from the random access memory and for producing therefrom the binary data streams B and N.

29. 发明授权

EP0785503B1 Procédé de production d'un paramètre de correction d'erreur associé à la mise en oeuvre d'opérations modulaires selon la méthode de Montgomery 失效
标题翻译：一种用于相对于产生误差校正参数根据所述蒙哥马利方法使用模运算的过程
公开(公告)号：EP0785503B1
公开(公告)日：1998-07-01
申请号：EP96470024.9
申请日：1996-12-11
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Monier, Guy
IPC分类号： G06F7/72
CPC分类号： G06F7/728

30. 发明公开

EP0712072A1 Procédé de mise en oeuvre de réduction modulaire selon la méthode de Montgomery 失效转让
标题翻译：弗吉尼亚州祖尔·奥斯福伦
公开(公告)号：EP0712072A1
公开(公告)日：1996-05-15
申请号：EP95470039.9
申请日：1995-10-26
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Monier, Guy
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： L'invention concerne un procédé de mise en oeuvre de réduction modulaire selon la méthode de Montgomery, dans lequel :

une donnée binaire C est codée sur un nombre c de bits, regroupés en m' mots de k bits, avec m' et k entiers, m' étant tel que m' * k ≧ c > (m' - 1) * k,
une donnée binaire N non nulle est codée sur un nombre n de bits,

caractérisé en ce que pour produire C mod N, on met en oeuvre des étapes de production d'une donnée binaire J₀ associée à N, de production d'au moins une donnée binaire H de la forme 2 f(C, N) avec f(C, N) un entier représentatif de la taille de C et de la parité de N, et de fourniture d'une part de C, à l'entrée parallèle d'un circuit de multiplication (19) ayant une entrée série, une entrée parallèle, et une sortie série, et d'autre part de H à l'entrée série de ce même circuit de multiplication.
摘要翻译：两个双输入多路复用器（41,42）提供移位寄存器（10,12）并允许输入模（N）和起始位（O）。减法电路（27）具有一个输入端连接到一个寄存器（10）的输出，另一个连接到多路复用器（36）的输出端。复用器（36）具有一个输入端连接到地线，另一个输入端连接到第二移位寄存器（12）的输出端。输入由来自存储比较的电路（44）的信号（SC）选择，并从减法单元（40）和门（43）提供。

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