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21. 发明公开

EP0793272A2 A pad protection diode structure 失效
标题翻译： Anschlussflächenschutzstrukturmit Diode
公开(公告)号：EP0793272A2
公开(公告)日：1997-09-03
申请号：EP97301336.0
申请日：1997-02-27
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Blanchard, Richard A.
IPC分类号： H01L27/02
CPC分类号： H01L27/0255 , H01L27/0248
摘要： There is provided protection for a first pad of an integrated circuit, the integrated circuit having a second pad to receive a first supply voltage. A first region of a first conductivity type is coupled to the first pad; a second region of a second conductivity type is coupled to the second pad; a substrate of the second conductivity type contacts the first and second regions; and there is an epitaxial layer of the first conductivity type. An epitaxial region contacts the first and second regions. A first diode can be formed outside the substrate between the first and second pads through at least two of the first region, the second region, and the epitaxial region. The protection structure may include first and second portions, each portion having a different voltage threshold. The first diode can be formed through the second portion, but not the first portion.
摘要翻译：为集成电路的第一焊盘提供保护，该集成电路具有用于接收第一电源电压的第二焊盘。第一导电类型的第一区域耦合到第一焊盘; 第二导电类型的第二区域耦合到第二焊盘; 第二导电类型的衬底接触第一和第二区域; 并且存在第一导电类型的外延层。外延区域接触第一和第二区域。可以通过第一区域，第二区域和外延区域中的至少两个，在第一和第二焊盘之间的衬底外部形成第一二极管。保护结构可以包括第一和第二部分，每个部分具有不同的电压阈值。第一二极管可以通过第二部分而不是第一部分形成。

22. 发明公开

EP0780894A3 Method of forming submicron contacts and vias in an integrated circuit 失效
标题翻译：一种用于制备在集成电路亚微米通路和触点过程
公开(公告)号：EP0780894A3
公开(公告)日：1997-08-27
申请号：EP96309299.4
申请日：1996-12-19
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Liou, Fu-Tai , Zamanian, Mehdi
IPC分类号： H01L21/768
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A method of forming a small geometry via and a structure formed thereby in which an opening is formed partially through an insulating layer (16), sidewalls (26) formed in the opening, and the remaining insulating layer etched to expose an underlying conductive region (14). Alternatively a thick oxide (36') is formed in the opening and etched to form sidewalls (38). Alternatively, an etch stop layer (42) is formed between the insulating layer and conductive region and an opening formed exposing the etch stop layer. A sidewall spacer film (46) is formed over the insulating and etch stop layers. The etch stop and spacer layers are etched thereby forming a contiguous layer. Alternatively a second insulating layer (56) is formed over the etch stop layer (54). An opening is formed then the spacer film (66) is formed. An etch exposes a portion of first insulating layer (16). A second opening is formed in the first insulating layer.

23. 发明公开

EP0745859A3 Configurable probe pads to facilitate parallel testing of integrated circuit devices 失效
标题翻译：用于集成电路的容易平行测试配置的接触带
公开(公告)号：EP0745859A3
公开(公告)日：1997-08-06
申请号：EP96302949.1
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Brannigan, Michael Joseph , Lysinger, Mark Alan , McClure, David Charles
IPC分类号： G01R1/04
CPC分类号： G01R31/2884 , G01R31/2831 , G11C29/48
摘要： According to the present invention, parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by muitiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

24. 发明授权

EP0472266B1 A semiconductor memory with improved test mode 失效
标题翻译：半导体具有改进的测试模式
公开(公告)号：EP0472266B1
公开(公告)日：1997-07-30
申请号：EP91304951.6
申请日：1991-05-31
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Coker, Thomas Allyn
IPC分类号： G11C29/00
CPC分类号： G11C29/28 , G11C29/34 , G11C29/38

25. 发明授权

EP0506426B1 Integrated circuit metallization with zero contact enclosure requirements and method of making the same 失效
标题翻译：集成电路的金属化与壳体和方法，用于其制备的零接触的要求
公开(公告)号：EP0506426B1
公开(公告)日：1997-07-23
申请号：EP92302665.2
申请日：1992-03-26
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Chen, Fusen E. , Liou, Fu-Tai
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76865 , H01L21/76877 , H01L21/76885 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S438/97 , H01L2924/00

26. 发明公开

EP0747960A3 Memory masking for periphery salicidation of active regions 失效
标题翻译： Speerehermaskierung zur Silizidierung derperiphärenaktiven Bereiche
公开(公告)号：EP0747960A3
公开(公告)日：1997-07-02
申请号：EP96303780.9
申请日：1996-05-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Nguyen, Loi Ngoc
IPC分类号： H01L27/105
CPC分类号： H01L27/105
摘要： An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
摘要翻译：集成电路存储器制造工艺和结构，其中在存储器芯片的外围（以及可选地在地线上）执行腐蚀，而不是在存储器单元的晶体管上执行。

27. 发明公开

EP0747936A3 Method of fabricating an integrated circuit with silicided contacts 失效
标题翻译： Herstellungsverfahren von integrierten Schaltungen mit silizierten Kontakten
公开(公告)号：EP0747936A3
公开(公告)日：1997-07-02
申请号：EP96303779.1
申请日：1996-05-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Nguyen, Loi Ngoc
IPC分类号： H01L21/285
CPC分类号： H01L21/28518
摘要： The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monocrystalline silicon, to form a "salicided" active area with improved sheet and contact resistance. Preferably one silicide is a reaction product and the other is deposited.
摘要翻译：本发明通过使用具有两种不同组成的两种硅化物来提供改进的器件速度：一个硅化物覆盖在多晶硅栅极层上，以形成具有改善的薄层电阻的“多晶硅”层，另一个覆盖至少一些“活性” 单晶硅的区域，以形成具有改善的片和接触电阻的“含水”活性区。优选地，一个硅化物是反应产物，另一个沉积。

28. 发明公开

EP0766290A3 Method for forming controlled voids in interlevel dielectric 失效
标题翻译：在层间电介质中形成受控空隙的方法
公开(公告)号：EP0766290A3
公开(公告)日：1997-05-14
申请号：EP96306862.2
申请日：1996-09-20
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Singh, Abha R. , Balasinski, Artur P. , Li, Ming M.
IPC分类号： H01L21/31 , H01L23/532 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76819 , H01L21/31 , H01L21/76801 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.
摘要翻译：一种在半导体器件结构中基本上平坦的表面上方以受控方式形成含有密封空隙的厚层间介质层的方法以及根据这种方法形成的半导体结构。密封的空隙用于减小层间电容。多个金属信号线形成在整体平面化的绝缘体上。在金属信号线上以及在金属信号线之间形成的金属间距上沉积厚层的第一共形夹层介质。由于层间电介质的厚度，流动性质和沉积方式以及金属间距的纵横比，所以在第一共形层间电介质中在金属间距中形成空隙。然后将该层间电介质蚀刻或抛光回所需的厚度，这暴露了较宽的金属间距中的空隙，但不暴露较窄的金属间距中的空隙。可以选择回蚀刻以使所有空隙暴露。暴露的空隙用可流动的电介质填充，然后可以将电介质回蚀，从而在暴露的空隙中留下可流动的电介质。在第一共形夹层电介质上形成第二共形夹层介电层以进一步掩埋密封空隙，确保它们在进一步的工艺步骤中不暴露。第二共形夹层电介质可以形成在薄层中以允许可流动电介质保持在层间电介质结构的顶部附近以减少中毒过孔的可能性。

29. 发明授权

EP0437081B1 Redundancy for serial memory 失效
标题翻译：冗余串行存储器
公开(公告)号：EP0437081B1
公开(公告)日：1997-04-23
申请号：EP90314116.6
申请日：1990-12-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F11/20
CPC分类号： G11C29/86 , G11C8/04

30. 发明公开

EP0720228A3 Semiconductor connection structure and method 失效
标题翻译：化合物半导体的结构和方法
公开(公告)号：EP0720228A3
公开(公告)日：1997-02-26
申请号：EP95308801.0
申请日：1995-12-05
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Miller, Robert O. , Smith, Gregory C.
IPC分类号： H01L23/522
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.

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