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11. 发明公开

EP1026827A1 Apparatus and method for proctecting a circuit during hot plugging 有权
标题翻译： Vorrichtung und Verfahren zum Schutz einer unter Spannung steckbaren Schaltung
公开(公告)号：EP1026827A1
公开(公告)日：2000-08-09
申请号：EP99309462.2
申请日：1999-11-26
申请人： Altera Corporation
发明人： Mejia, Manuel
IPC分类号： H03K19/0185
CPC分类号： H03K19/003
摘要： A circuit includes an output node, a set of output transistors operative to control the signal level on the output node, a first voltage supply, and a second voltage supply. A hot socket detection circuit identifies when the first voltage supply or the second voltage supply is below a predetermined value indicative of a hot socket condition. In response to a hot socket condition, the hot socket detection circuit generates control signals that place the set of output transistors in a high impedance state.
摘要翻译：电路包括输出节点，用于控制输出节点上的信号电平的一组输出晶体管，第一电压源和第二电压源。热插座检测电路识别第一电压源或第二电压供应何时低于指示热插座状况的预定值。响应于热插座状况，热插座检测电路产生将该组输出晶体管置于高阻抗状态的控制信号。

12. 发明授权

EP0476341B1 A BICMOS logic circuit with a CML output 失效
标题翻译： BICMOS逻辑电路具有一个输出CML
公开(公告)号：EP0476341B1
公开(公告)日：1997-01-15
申请号：EP91114028.3
申请日：1991-08-22
申请人： MOTOROLA, INC.
发明人： Huehne, Karl Jackson
IPC分类号： H03K19/20 , H03K19/0175 , H03K19/086
CPC分类号： H03K19/09448 , H03K19/003

13. 发明公开

EP0664615A2 An ECL to CMOS signal converter circuit including toggle-fault detection 失效转让
标题翻译： ECL到CMOS信号转换器电路，包括触发故障检测
公开(公告)号：EP0664615A2
公开(公告)日：1995-07-26
申请号：EP95100679.0
申请日：1995-01-19
申请人： ALCATEL N.V.
发明人： Ruegg, Eugen H.
IPC分类号： H03K19/003 , H03K19/0175 , H03K5/007 , H04L25/02 , H04L1/24
CPC分类号： H03K19/003 , H03K19/017509
摘要： An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer (420) is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit (CR₁,CR₂) shifts the average DC level of the CMOS level signals in a positive direction to avoid signal undershoot. An AC peak detection circuit is connected to the inactive leg (A) of the RF transformer (420) to monitor toggling of the ECL level input signal lines. A DC comparator circuit (430) compares the detected peak voltage with a predetermined threshold voltage, and generates an alarm signal representing a toggle-fault whenever the detected peak voltage is lower than the predetermined threshold.
摘要翻译：提供了包括内置触发故障检测电路和转换方法的ECL到CMOS信号转换器电路，其中使用RF变压器（420）将ECL电平数字信号转换成CMOS电平信号。二极管偏置电路（CR 1，CR 2）将CMOS电平信号的平均DC电平沿正方向移动以避免信号下冲。 AC峰值检测电路连接到RF变压器（420）的无源臂（A）以监视ECL电平输入信号线的切换。 DC比较器电路（430）将检测到的峰值电压与预定阈值电压进行比较，并且无论何时检测到的峰值电压低于预定阈值，都生成表示触发故障的警报信号。

14. 发明公开

EP0598475A3 Apparatus and method for protecting a programmable logic device from undesired input overshoot voltages 失效
标题翻译：装置和用于保护的可编程逻辑电路过电压的方法。
公开(公告)号：EP0598475A3
公开(公告)日：1995-03-22
申请号：EP93307049.2
申请日：1993-09-07
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Chang, Herman M. , Sharpe-Geisler, Bradley
IPC分类号： H03K19/003 , H03K19/177 , G11C16/06 , G11C7/00
CPC分类号： H03K19/17764 , G11C7/24 , G11C16/225 , H03K19/003 , H03K19/1778
摘要： A device for protecting a programmable logic device from undesired input overshoot voltages. The invention requires the overvoltage to be applied for a time duration longer than the predetermined time constant of a time delay circuit. The time delay distinguishes between the undesired overvoltages which are less than the predetermined time delay and are rejected as noise induced from the desired overvoltages which exceed the predetermined time delay and are recognized as intentional programming "super voltages". The invention is used to protect programmable logic devices, such as programmable arrays, from inadvertently entering into an erasable or programmable mode of the logic device, such as, the edit mode.

15. 发明公开

EP0598475A2 Apparatus and method for protecting a programmable logic device from undesired input overshoot voltages 失效
标题翻译：装置和用于保护的可编程逻辑电路过电压的方法。
公开(公告)号：EP0598475A2
公开(公告)日：1994-05-25
申请号：EP93307049.2
申请日：1993-09-07
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Chang, Herman M. , Sharpe-Geisler, Bradley
IPC分类号： H03K19/003 , H03K19/177 , G11C16/06 , G11C7/00
CPC分类号： H03K19/17764 , G11C7/24 , G11C16/225 , H03K19/003 , H03K19/1778
摘要： A device for protecting a programmable logic device from undesired input overshoot voltages. The invention requires the overvoltage to be applied for a time duration longer than the predetermined time constant of a time delay circuit. The time delay distinguishes between the undesired overvoltages which are less than the predetermined time delay and are rejected as noise induced from the desired overvoltages which exceed the predetermined time delay and are recognized as intentional programming "super voltages". The invention is used to protect programmable logic devices, such as programmable arrays, from inadvertently entering into an erasable or programmable mode of the logic device, such as, the edit mode.
摘要翻译：一种用于保护可编程逻辑器件免受不期望的输入电压的过冲装置。本发明需要过电压到对于持续时间大于一个时间延迟电路的预定的时间常数而施用的更长。延时区分不需要过电压哪些是小于预定的时间延迟，被拒绝从期望中的过电压超出了预定的时间延迟，并被认为是故意设计的“超电压”引起的噪声之间。本发明是用来保护可编程逻辑器件，颜色：如可编程阵列，从无意中进入的逻辑器件，彩色的可擦除或可编程模式：例如，编辑模式。

16. 发明授权

EP0173744B1 FUNCTIONALLY REDUNDANT LOGIC NETWORK ARCHITECTURES WITH LOGIC SELECTION MEANS 失效
标题翻译：功能冗余逻辑网络架构与逻辑选择手段
公开(公告)号：EP0173744B1
公开(公告)日：1991-09-11
申请号：EP85901763.4
申请日：1985-03-14
申请人： AEROJET-GENERAL CORPORATION , THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： MOORE, Donald W. , VERSTRAETE, Rik
IPC分类号： H03K19/003
CPC分类号： H03K19/1733 , H03K19/003 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17764
摘要： A programmable gate structure (20) having functionally redundant architeture for enhanced production yields and reliability comprises a plurality of two-input nodes (10) at least some of which may be programmed by control states (24, 26 and 28) for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for reprogramming in response to detected faults to achieve a desired gate function. A number of embodiments are disclosed including selected architectural simplifications wherein certain nodes in a network are logically fixed to reduce the number of control lines. Illustrative computer programs for generating the proper control line signals for a selected gate function in such embodiments are disclosed.

17. 发明授权

EP3732814B1 QUANTITATIVE DIGITAL SENSOR 有权转让
公开(公告)号：EP3732814B1
公开(公告)日：2024-10-30
申请号：EP18803696.6
申请日：2018-11-21
IPC分类号： H04L9/00 , G06F21/75 , G06F21/55 , H01L23/00 , G01R31/28 , G01R31/317 , H03K19/003
CPC分类号： G01R31/31719 , G06F21/55 , G06F21/75 , H01L23/576 , H03K19/003 , H04L9/004 , G06F2207/721920130101 , G06F2207/727120130101 , H04L2209/1220130101

18. 发明公开

EP4360013A1 APPARATUS AND METHOD FOR COHERENT ERROR MITIGATION USING CLIFFORD GATE INJECTION 审中-实审
公开(公告)号：EP4360013A1
公开(公告)日：2024-05-01
申请号：EP22828948.4
申请日：2022-04-01
申请人： Intel Corporation
发明人： PREMARATNE, Shavindra , SCHMITZ, Albert , MATSUURA, Anne , ZOU, Xiang
IPC分类号： G06N10/70 , G06N10/20
CPC分类号： H03K19/003 , G06F8/41 , G06F11/0793 , G06N10/70 , G06N10/20 , G06N10/80

19. 发明公开

EP3404791A1 APPARATUS AND METHODS FOR OVERVOLTAGE PROTECTION OF ELECTRONIC DEVICES 有权
公开(公告)号：EP3404791A1
公开(公告)日：2018-11-21
申请号：EP18170253.1
申请日：2018-05-01
申请人： Eaton Intelligent Power Limited
发明人： NOJIMA, Geraldo
IPC分类号： H02H9/04
CPC分类号： H02H9/042 , H02H3/20 , H02H7/205 , H02H9/002 , H02H9/041 , H02H9/044 , H02M1/08 , H03K19/003
摘要： An apparatus includes a string of series-connected voltage clamp devices (e.g., metal-oxide varistors (MOVs)) coupled to at least one electronic device (e.g., a transistor or other semiconductor device). The apparatus further includes a bypass circuit configured to selectively bypass a subset of the string of series-connected voltage clamp devices to control a level at which a voltage applied to the at least one electronic device is clamped. A control circuit may be configured to cause the bypass circuit to bypass the subset of the string of series-connected voltage clamp devices responsive to a voltage applied to the at least one electronic device. For example, the control circuit may be configured to cause the bypass circuit to bypass the subset of the string of series-connected voltage clamp devices responsive to a magnitude of the voltage applied to the at least one electronic device exceeding a threshold.

20. 发明公开

EP3322094A1 CONSTANT-VOLTAGE GENERATING APPARATUS AND MEASURING APPARATUS 无效
标题翻译：恒定电压发生装置和测量装置
公开(公告)号：EP3322094A1
公开(公告)日：2018-05-16
申请号：EP17192928.4
申请日：2017-09-25
申请人： Fuji Electric Co., Ltd.
发明人： YOSHIMURA, Hiroyuki
IPC分类号： H03K19/003
CPC分类号： G05F1/575 , G05F1/468 , H03K19/003
摘要： A constant-voltage generating apparatus including a plurality of constant-voltage circuits connected in series is provided. Each of the constant-voltage circuits has a positive-side power supply node, a negative-side power supply node, and a control unit that controls voltage between the positive-side power supply node and the negative-side power supply node to be constant voltage. The positive-side power supply node in the constant-voltage circuit at a preceding stage is connected to the negative-side power supply node in the constant-voltage circuit at a subsequent stage. The constant-voltage generating apparatus may further include a constant-current circuit that regulates power-supply currents flowing through the plurality of constant-voltage circuits to be constant.
摘要翻译：提供了包括串联连接的多个恒压电路的恒压产生装置。每个恒压电路具有正侧电源节点，负侧电源节点以及控制单元，该控制单元将正侧电源节点和负侧电源节点之间的电压控制为恒定电压。前级恒压电路中的正侧电源节点连接到后级的恒压电路中的负侧电源节点。恒压产生装置还可以包括恒流电路，该恒流电路将流过多个恒压电路的电源电流调节为恒定。

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