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11. 发明公开

EP2401761A4 INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION 审中-公开
标题翻译：与深沟槽隔离区法分离之间和国家内部孔，并用共享联系人FOR间扩散区域之上的连接之间的相邻设备及A的下方浮动井段的集成电路器件
公开(公告)号：EP2401761A4
公开(公告)日：2012-04-25
申请号：EP10780978
申请日：2010-05-04
申请人： IBM
发明人： ANDERSON BRENT A , BRYANT ANDRES , NOWAK EDWARD J
IPC分类号： H01L21/8244 , H01L21/8234 , H01L27/11
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104

12. 发明公开

EP2086005A3 Semiconductor device 审中-公开
公开(公告)号：EP2086005A3
公开(公告)日：2012-03-14
申请号：EP08253677.2
申请日：2008-11-10
申请人： Renesas Electronics Corporation
发明人： Maeda, Noriaki
IPC分类号： H01L27/088 , H01L27/092 , H01L27/02 , H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0207 , H01L27/092 , H01L27/1104
摘要： A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

13. 发明公开

EP2368267A2 TRIGATE STATIC RANDOM-ACCESS MEMORY WITH INDEPENENT SOURCE AND DRAIN ENGINEERING, AND DEVICES MADE THEREFROM 有权
标题翻译： WITH由其得到UNITS独立的输入和输出处理与产品STATIC TRI-GATE DIRECT ACCESS MEMORY
公开(公告)号：EP2368267A2
公开(公告)日：2011-09-28
申请号：EP09835519.1
申请日：2009-12-09
申请人： Intel Corporation
发明人： PILLARESITTY, Ravi , RACHMADY, Willy , DOYLE, Brian , CHAU, Robert S.
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/845 , H01L27/11 , H01L27/1211
摘要： A static random-access memory (SRAM) circuit includes at least one access device on a first N-type fin (222) including source and drain sections for a pass region, at least one pull-up device on a P-type fin (226), and at least one pull-down device on a second N-type fin (222) including source-and-drain sections for a pull-down region. The SRAM circuit further comprises epitaxial structures (230, 236) on the source and drain sections of the pass and the pull-down devices, wherein the volume of the epitaxial structures on the source section and the drain section of the pass device (230) differs from the volume of the epitaxial structures on the source and drain section of the pull-down device (236) such that the external resistivity (Rext) for the pull-down region is lower than Rext for the pass region.

14. 发明公开

EP2293327A1 Circuit intégré à transistors MOS couplés électrostatiquement et procédé de réalisation d'un tel circuit intégré 审中-公开
标题翻译：一种集成电路，包括静电耦合的MOS晶体管，以及制造其的方法
公开(公告)号：EP2293327A1
公开(公告)日：2011-03-09
申请号：EP10174497.7
申请日：2010-08-30
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Augendre, Emmanuel , Vinet, Maud , Clavelier, Laurent , Batude, Perrine
IPC分类号： H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/49
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： Circuit intégré (100) comportant :
- un premier transistor (101a) ;
- un second transistor (101b), disposé sur le premier transistor, dont une région de canal (109b) est formée dans une couche (104b) de semi-conducteur comportant deux faces principales (106b, 108b) sensiblement parallèles ;
- une portion (117) d'un matériau électriquement conducteur reliée électriquement à une grille (113a) du premier transistor et disposée entre la grille du premier transistor et la région de canal du second transistor ;
- une couche (103) diélectrique disposée entre la portion du matériau électriquement conducteur et la région de canal du second transistor ;

et dans lequel
la section de la région de canal du second transistor est incluse dans la section de la portion du matériau électriquement conducteur, et
la région de canal du second transistor est disposée entre la portion du matériau électriquement conducteur et une grille du second transistor.
摘要翻译：所述电路（100）具有较低的MOS晶体管（101A）和上MOS晶体管（101B）的沟道区域（109B）中的一个栅极之间放置导电部分（117）（113A）。介电层（103）在导电部和沟道区之间放置。沟道区的部分位于平行于半导体层（104B）的主表面（106B，108B）的平面和包括在所述导电部分的一个部分。上晶体管的沟道区域上晶体管的导电部分和栅极（113B）之间放置。因此独立claimsoft包括用于形成集成电路上的方法。

15. 发明公开

EP2254149A2 SRAM using vertical transistors with a diffusion layer for reducing leakage currents 有权转让
标题翻译：移动电话传输系统扩散系统Verminderung vonLeckströmen
公开(公告)号：EP2254149A2
公开(公告)日：2010-11-24
申请号：EP10005356.0
申请日：2010-05-21
申请人： Unisantis Electronics (Japan) Ltd.
发明人： Masuoka, Fujio , Arai, Shintaro
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/1083 , H01L27/0886 , H01L27/11 , H01L27/1104 , H01L29/66666 , H01L29/7827
摘要： In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain (4a), gate (18) and source (16) formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer (23a), the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer (13a) formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well (1a) positioned on the substrate are surrounded by a first anti-leak diffusion layer (1b) and a second anti-leak diffusion layer (1c) having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.
摘要翻译：在包括六个MOS晶体管的静态存储单元中，MOS晶体管具有其中形成在衬底上的漏极（4a），栅极（18）和源极（16）在垂直方向上排列并且栅极围绕柱状半导体层（23a），衬底包括具有第一导电类型的第一有源区和具有第二导电类型的第二有源区，并且构成有源区的扩散层通过形成在衬底表面上的硅化物层（13a）相互连接从而实现具有小表面积的SRAM单元。此外，具有与位于基板上的第一阱（1a）相同的导电类型的漏扩散层由具有导电类型的第一防漏扩散层（1b）和第二防漏扩散层（1c）包围与第一阱不同，并且比第一阱浅，从而控制对基板的泄漏。

16. 发明授权

EP1939888B1 Cellule mémoire dotée de transistors double-grille, à grilles indépendantes et asymétriques 有权
标题翻译：存储器单元配备有具有双栅极的，独立的和非对称的栅极的晶体管
公开(公告)号：EP1939888B1
公开(公告)日：2010-09-15
申请号：EP07123410.8
申请日：2007-12-17
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Thomas, Olivier , Vinet, Maud
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , H01L29/785

17. 发明公开

EP1943671A4 MULTIPLE DEVICE TYPES INCLUDING AN INVERTED-T CHANNEL TRANSISTOR AND METHOD THEREFOR 审中-公开
标题翻译：多种元素，包括一个倒T型沟道晶体管及其方法
公开(公告)号：EP1943671A4
公开(公告)日：2009-12-30
申请号：EP06816683
申请日：2006-10-10
申请人： FREESCALE SEMICONDUCTOR INC
发明人： MIN BYOUNG W , BURNETT JAMES D , MATHEW LEO
IPC分类号： H01L21/4763 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785

18. 发明公开

EP2104951A1 PROCEDE DE REALISATION DE TRANSISTORS A DOUBLE-GRILLE ASYMETRIQUES PERMETTANT LA REALISATION DE TRANSISTORS A DOUBLE-GRILLE ASYMETRIQUES ET SYMETRIQUES SUR UN MEME SUBSTRAT 有权
标题翻译：用于生产非对称和对称双栅极晶体管在同一衬底
公开(公告)号：EP2104951A1
公开(公告)日：2009-09-30
申请号：EP07858219.4
申请日：2007-12-28
申请人： Commissariat à l'Energie Atomique
发明人： VINET, Maud , THOMAS, Olivier , ROZEAU, Olivier , POIROUX, Thierry
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L29/78645
摘要： The invention relates to a method for producing a microelectronic device with one or more symmetric and asymmetric double-gate transistors on the same substrate.

19. 发明授权

EP1292979B1 METHOD FOR A DIRECT BURIED STRAP FOR SAME LEVEL INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES 有权
标题翻译：程序对直埋连接带为进行在同一级别的连接半导体器件
公开(公告)号：EP1292979B1
公开(公告)日：2009-08-19
申请号：EP01948582.0
申请日：2001-06-21
申请人： Infineon Technologies AG
发明人： STETTER, Michael , GRELLNER, Frank
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/28518 , H01L27/1104
摘要： A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack (106) on a semiconductor substrate (102), and forming a protective layer on sidewalls (108) of the gate stack. The protective layer extends horizontally (109) over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer (112) is formed over the protective layer and in contact with a gate conductor (107) of the gate stack and in contact with a diffusion region (104) formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap (120) and a silicided diffusion region (114) in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.

20. 发明公开

EP2075831A2 Semiconductor device with shared contact hole for gate electrode and drain region 审中-公开
标题翻译： Halbleitervorrichtung mit geteiltem KontaktlochfürGate-Elektrode und Drain-Gebiet
公开(公告)号：EP2075831A2
公开(公告)日：2009-07-01
申请号：EP08254137.6
申请日：2008-12-23
申请人： Renesas Technology Corp.
发明人： Takeuchi, Masahiko , Renesas Technology Corp.
IPC分类号： H01L21/8239 , H01L21/8244 , H01L27/02 , H01L27/105 , H01L27/11 , H01L21/027 , H01L21/768
CPC分类号： H01L27/1104 , H01L21/76895 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L29/4238
摘要： Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line (C2-C2) of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line (C1-C1) of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device such as an SRAM or TCAM and a photomask that can suppress an opening defect of the shared contact hole are obtained.
摘要翻译：共用接触孔SC1和SC2到达栅极电极层GE1和GE2以及漏极区PIR。在平面图中，栅电极层GE1和GE2的侧壁E2从侧壁E1的虚拟延伸线E1a向侧壁E4侧移动。在平面图中，在共享栅极电极层GE1和GE2的接触孔SC1和SC2的共享部分中的线宽度D1的中心线（C2-C2）位于相对于中心线（C1-C1 ）位于栅极电极层GE1和GE2的沟道形成区域CHN1和CHN2的部分中的线宽度D2。因此，可以获得诸如SRAM或TCAM的半导体器件和可以抑制共享接触孔的开口缺陷的光掩模。

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