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11. 发明公开

EP1617469A2 Semiconductor device having copper wiring and its manufacturing method 审中-公开
标题翻译：具有铜布线，及它们的制备方法的半导体器件
公开(公告)号：EP1617469A2
公开(公告)日：2006-01-18
申请号：EP05254190.1
申请日：2005-07-04
申请人： FUJITSU LIMITED
发明人： Koura, Yumiko c/o FUJITSU LIMITED , Kitada, Hideki c/o FUJITSU LIMITED
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/2885 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A first interlayer insulating film (10) made of insulating material is formed over an underlying substrate (1). A via hole is formed through the first interlayer insulating film. A conductive plug (13) made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film (15) made of insulating material is formed over the first interlayer insulating film (10). A wiring groove is formed in the second interlayer insulating film (15), passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring (17) made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atomic concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atomic concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.

12. 发明公开

EP1519411A2 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：EP1519411A2
公开(公告)日：2005-03-30
申请号：EP04022445.3
申请日：2004-09-21
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Hashimoto, Shin , Mimura, Tadaaki
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5226 , H01L23/53228 , H01L24/03 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01074 , H01L2924/01082 , H01L2924/00014
摘要： A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.
摘要翻译：一种半导体器件，包括：形成在半导体衬底上的第一绝缘膜;形成在第一绝缘膜上的第一金属图案;形成在第一金属图案上的第二绝缘膜;形成在第二绝缘膜上的第二金属图案;以及第三金属图案，形成在第二绝缘膜中并且连接在第一金属图案和第二金属图案之间。第三金属图案是单一连续结构，并且构成第三金属图案的金属的晶体的主取向轴线平行于半导体衬底的主表面。

13. 发明公开

EP1126519A3 Structure and method for bond pads of copper-metallized intergrated circuits 审中-公开
标题翻译：对intergrierten电路镀铜垫结构和制造方法
公开(公告)号：EP1126519A3
公开(公告)日：2004-02-18
申请号：EP01000021.4
申请日：2001-02-19
申请人： Texas Instruments Incorporated
发明人： Stierman, Roger J. , Amador, Gonzalo , Test, Howard R.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/0518 , H01L2224/05184 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4845 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/78301 , H01L2224/85043 , H01L2224/85045 , H01L2224/85201 , H01L2224/85205 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/3025 , H01L2924/00014 , H01L2924/01004 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2224/29099 , H01L2924/00015 , H01L2924/013
摘要： A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1 x 10E-23 cm 2 /s at 250 °C and a thickness from about 0.5 to 1.5 µm. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1 x 10E-14 cm 2 /s at 250 °C and a thickness of less than 1.5 µm. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost metal layer is selected from a group consisting of gold, platinum, and silver.

14. 发明公开

EP1146558A3 Damascene wiring structure and semiconductor device with damascene wirings 有权
标题翻译：大马士革Verdrahtung Struktur und Halbleiterement mit大马士革Verdrahtungen
公开(公告)号：EP1146558A3
公开(公告)日：2003-11-05
申请号：EP01300116.9
申请日：2001-01-08
申请人： FUJITSU LIMITED
发明人： Otsuka, Satoshi , Yamanoue, Akira
IPC分类号： H01L23/532 , H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A damascene wiring structure having: a lower wiring structure (5); an interlayer insulating film (7) covering the lower wiring structure (5); a wiring trench (G2) formed in the interlayer insulating film (7) from an upper surface thereof, and a via hole (VIA) passing through the interlayer insulating film (7) from a lower surface of the wiring trench (G2) in an inner area thereof and reaching the lower wiring structure (5), the via hole (VIA) having a diameter smaller than a width of the wiring trench (G2); an insulating pillar pattern (RI) projecting upward from the lower surface of the wiring trench (G2) in an area outside of the via hole (VIA), the insulating pillar pattern (RI) being made of a same material as the interlayer insulating film (7), wherein a first occupied area factor of the insulating pillar pattern (RI) in a first area of the wiring trench (G2) near said via hole (VIA) is higher than a second occupied area factor of the insulating pillar pattern (RI) in a second area of the wiring trench (G2) remote from the via hole (VIA); and a dual damascene wiring (10) formed by filling the wiring trench (G2) and said via hole (G2) with conductive material. A damascene wiring structure (10) having a high reliability and a semiconductor device having such a damascene wiring structure can be formed.
摘要翻译：一种镶嵌式布线结构，具有：下部布线结构（5）; 覆盖下部布线结构（5）的层间绝缘膜（7）; 从上表面形成在层间绝缘膜（7）中的布线沟槽（G2）和从布线沟槽（G2）的下表面穿过层间绝缘膜（7）的通孔（VIA）其内部区域到达下部布线结构（5），所述通孔（VIA）的直径小于所述布线沟槽（G2）的宽度; 绝缘柱图案（RI），其从所述布线沟槽（G2）的下表面向上突出在所述通孔（VIA）外的区域中，所述绝缘柱图案（RI）由与所述层间绝缘膜相同的材料制成（7），其中在所述通孔（VIA）附近的布线沟槽（G2）的第一区域中的绝缘柱图案（RI）的第一占有面积因子高于绝缘柱图案的第二占据面积因子 RI），远离通孔（VIA）的布线沟槽（G2）的第二区域中; 以及通过用导电材料填充所述布线沟槽（G2）和所述通孔（G2）而形成的双镶嵌布线（10）。可以形成具有高可靠性的镶嵌布线结构（10）和具有这种镶嵌布线结构的半导体器件。

15. 发明公开

EP1346408A2 INTERCONNECT STRUCTURES AND A METHOD OF ELECTROLESS INTRODUCTION OF INTERCONNECT STRUCTURES 有权
标题翻译：程序将中间结构的外部电源的地段简介
公开(公告)号：EP1346408A2
公开(公告)日：2003-09-24
申请号：EP01993180.7
申请日：2001-11-15
申请人： INTEL CORPORATION
发明人： MCGREGOR, Paul, J. , THOMAS, Christopher , DATTA, Madhav , DUBIN, Valery
IPC分类号： H01L21/768 , H01L21/288
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76873 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point a point (120) a nd introducing a conductive shunt material (180) through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, introducing a conductive shunt material having an oxidation number over an exposed surface of the interconnect structure, and reducing the oxidation number of the shunt. An apparatus comprising a substrate comprising a device having contact point, a dielectric layer (130) overlying the device with an opening to the contact point (120), and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material (180).

16. 发明公开

EP1340252A2 OPTIMIZED LINERS FOR DUAL DAMASCENE METAL WIRING 审中-公开
标题翻译：最佳AUSKLEIDUNGFÜRDOPPEL-DAMASZENER VERDRAHTUNG
公开(公告)号：EP1340252A2
公开(公告)日：2003-09-03
申请号：EP01998019.2
申请日：2001-10-31
申请人： Tokyo Electron Limited
发明人： HILLMAN, Joseph, T.
IPC分类号： H01L21/768
CPC分类号： H01L21/76831 , H01L21/76846 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an electrically resistive diffusion barrier are deposited on a dielectric substrate, with different layers having different thicknesses appropriate to their functions in the device. In an example of the present invention, alternating layers of tantalum and tantalum nitride are deposited on a dielectric substrate.
摘要翻译：在用于双金属镶嵌金属芯片级互连的电介质上形成扩散势垒叠层的方法，以及由此产生的扩散阻挡叠层。金属和电阻扩散阻挡层的交替层被沉积在电介质基底上，其中不同的层具有适合其在器件中的功能的不同厚度。在本发明的一个实例中，钽和氮化钽的交替层沉积在电介质基片上。

17. 发明公开

EP1077483A3 Method of making an integrated circuit device having a planar interlevel dielectric layer 审中-公开
标题翻译：一种用于制造具有平面介质中间层的集成电路处理
公开(公告)号：EP1077483A3
公开(公告)日：2003-02-05
申请号：EP00306709.7
申请日：2000-08-07
申请人： LUCENT TECHNOLOGIES INC.
发明人： Abdelgadir, Mahjoub Ali , Maury, Alvaro
IPC分类号： H01L21/768 , H01L21/316 , H01L23/532
CPC分类号： C23C14/083 , C23C14/5806 , C23C14/5873 , H01L21/28167 , H01L21/31612 , H01L21/31629 , H01L21/76801 , H01L21/76819 , H01L21/76837 , H01L21/76888 , H01L23/5222 , H01L23/5223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L28/60 , H01L29/51 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes depositing a conductive layer, having conductive lines (32) with gaps (40) therebetween, adjacent a semiconductor substrate (30). A fluoro-silicate glass (FSG) layer (36) is deposited by high-density plasma chemical vapor deposition (HDP-CVD), over the patterned conductive layer and to fill the gaps between conductive lines. The method further includes chemically mechanically polishing the FSG layer and depositing an undoped oxide (38) layer on the FSG layer. Peaks of the FSG layer which correspond to the widths of the conductive metal lines are reduced by the CMP step. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.

18. 发明公开

EP1197586A3 Electrolyte 审中-公开
标题翻译：电解质
公开(公告)号：EP1197586A3
公开(公告)日：2002-09-25
申请号：EP01308710.1
申请日：2001-10-12
申请人： Shipley Company LLC
发明人： Morrissey, Denis , Mikkola, Robert D. , Calvert, Jeffrey M.
IPC分类号： C25D3/38 , C25D5/48 , B24B37/04 , H01L21/768 , H01L21/321 , H01L23/532
CPC分类号： C25D3/38 , C25D5/48 , H01L21/3212 , H01L23/53228 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： Disclosed are electrolytes for copper electroplating that provide enhanced fill of small features with less overplate. Also disclosed are methods of plating substrates, such as electronic devices, using such electrolytes.

19. 发明公开

EP1228530A1 METAL REDISTRIBUTION LAYER HAVING SOLDERABLE PADS AND WIRE BONDABLE PADS 审中-公开
标题翻译：金属加工麻省理工学院麻省理工学院
公开(公告)号：EP1228530A1
公开(公告)日：2002-08-07
申请号：EP00961480.1
申请日：2000-08-31
申请人： ATMEL CORPORATION
发明人： LAM, Ken, M. , KOVATS, Julius, A.
IPC分类号： H01L23/525 , H01L23/532
CPC分类号： H01L24/10 , H01L23/525 , H01L23/53228 , H01L23/53238 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2224/48463 , H01L2224/731 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A redistribution metallization scheme combines solder bumps (122) and wire bond pads (132) in addition to existing bond pads (102) to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals (204, 206, 208) used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.
摘要翻译：再分布金属化方案除了现有的接合焊盘之外还结合了焊料凸块和引线接合焊盘，以增强半导体器件的连接性，特别是在倒装芯片应用中。制造方法包括在再分布沉积步骤期间形成附加的接合焊盘。在再分配层中使用的金属提供用于焊料凸起的可焊接表面和用于引线接合的可粘合表面。

20. 发明公开

EP1112125A2 METALLIZATION STRUCTURES FOR MICROELECTRONIC APPLICATIONS AND PROCESS FOR FORMING THE STRUCTURES 有权
标题翻译：金属化用于生产这种结构的微电子应用和方法
公开(公告)号：EP1112125A2
公开(公告)日：2001-07-04
申请号：EP99932154.0
申请日：1999-06-30
申请人： SEMITOOL, INC.
发明人： KRISHNAMOORTHY, Ahila , DUQUETTE, David, J. , MURARKA, Shyam, P.
IPC分类号： B05D3/10 , B32B15/06 , B32B15/18 , B32B19/00 , B32B9/00
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/12 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76877 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metallized structure (20) for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, and a low-Me concentration, copper-Me alloy layer (40) disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor (43), such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

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