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11. 发明授权

EP2911056B1 METHOD FOR REDUCING CONSUMPTION OF MEMORY SYSTEM AND MEMORY CONTROLLER 有权
公开(公告)号：EP2911056B1
公开(公告)日：2018-07-18
申请号：EP12886768.6
申请日：2012-10-17
申请人： Huawei Technologies Co., Ltd.
发明人： HUANG, Yongbing , CHEN, Mingyu , RUAN, Yuan
IPC分类号： G06F12/06 , G06F3/06 , G06F1/32 , G06F9/50
CPC分类号： G06F1/3225 , G06F1/3275 , G06F3/0625 , G06F3/0647 , G06F3/068 , G06F9/5016 , G06F9/5094 , G06F12/0638 , G06F2212/1028 , G06F2212/205 , G06F2212/251 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/22 , Y02D50/20
摘要： Embodiments of the present invention provide a method for reducing power consumption of a memory system and a memory controller. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time. According to the embodiments of the present invention, the page data other than the working set is transferred to the NVM memory module, and because the NVM memory module has characteristics of non-volatility and low-power consumption, transferring a part of data in the DRAM memory module to the NVM memory module may reduce the power consumption of the whole memory system.

12. 发明公开

EP3239844A4 PROCESSING METHOD AND DEVICE FOR MEMORY PAGE IN MEMORY 有权
公开(公告)号：EP3239844A4
公开(公告)日：2017-12-20
申请号：EP15877626
申请日：2015-09-25
申请人： HUAWEI TECH CO LTD
发明人： LIU DUO , SHAO ZILI , LONG LINBO
IPC分类号： G06F12/02 , G06F12/122
CPC分类号： G06F12/122 , G06F12/02 , G06F12/0246 , G06F2212/1036 , G06F2212/251 , G06F2212/7208
摘要： The present invention relates to the field of storage technologies, and in particular, to a method and an apparatus for processing a memory page in memory, to obtain relatively high access performance and a relatively large storage capacity. In the method for processing a memory page in memory provided in the present invention, the memory page in the memory includes an idle single-level cell SLC memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell MLC memory page; and the processing method includes: when determining that a quantity of idle single-level cell SLC memory pages of any virtual machine VM is less than a specified threshold, converting one idle SLC memory page to two MLC memory pages; copying data in two inactive SLC memory pages to the two converted MLC memory pages; and releasing storage space of the two inactive SLC memory pages, to obtain two idle SLC memory pages.

13. 发明公开

EP3234769A1 TRACE BUFFER BASED REPLAY FOR CONTEXT SWITCHING 审中-公开
标题翻译：基于TRACE BUFFER的上下文切换
公开(公告)号：EP3234769A1
公开(公告)日：2017-10-25
申请号：EP15816988.8
申请日：2015-12-02
申请人： Qualcomm Incorporated
发明人： ACHARYA, Anirudh Rajendra
IPC分类号： G06F9/38
CPC分类号： G06F13/24 , G06F9/3808 , G06F9/3832 , G06F9/3851 , G06F9/3863 , G06F9/3879 , G06F9/461 , G06F11/00 , G06F12/023 , G06F2212/251 , G06T1/20
摘要： A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more operations in the command stream in a trace buffer, wherein the first set of one or more operations accesses one or more memory locations in memory, and wherein the data include an indication of contents of the one or more memory locations associated with the first set of one or more operations. The command processor may interrupt the processing of the command stream. The command processor may, in response to resuming processing of the command stream subsequent to the interrupting of the processing of the command stream, replay at least a portion of the command stream, including processing a second set of one or more operations of the command stream based at least in part on the data stored in the trace buffer.
摘要翻译：命令处理器可处理用于由至少一个处理器执行的命令流，包括将与命令流中的第一组一个或多个操作相关联的数据存储在跟踪缓冲器中，其中第一组一个或多个操作访问一个或多个操作存储器中更多的存储器位置，并且其中数据包括与第一组一个或多个操作相关联的一个或多个存储器位置的内容的指示。命令处理器可能中断命令流的处理。命令处理器可以响应于在中断命令流的处理之后恢复命令流的处理，重放命令流的至少一部分，包括处理命令流的一个或多个操作的第二集合至少部分基于存储在跟踪缓冲器中的数据。

14. 发明公开

EP3214545A1 EMBEDDED DEVICE AND PROGRAM UPDATING METHOD 有权
标题翻译：嵌入式设备和程序更新方法
公开(公告)号：EP3214545A1
公开(公告)日：2017-09-06
申请号：EP17158031.9
申请日：2017-02-27
申请人： Renesas Electronics Corporation
发明人： TANIMOTO, Tadaaki , HAGIWARA, Kesami , MORITA, Naoyuki
IPC分类号： G06F9/44 , G06F9/445 , G06F12/02 , G06F9/32
CPC分类号： G06F8/65 , G06F8/654 , G06F8/658 , G06F9/32 , G06F9/44521 , G06F12/02 , G06F12/0292 , G06F2212/251 , H04L67/34
摘要： An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.
摘要翻译：本发明的一个目的是在不使用更新前程序和更新差别程序来重建程序的情况下执行程序更新处理。嵌入式设备具有非易失性存储器，该非易失性存储器具有可独立读取/写入数据的多个平面以及通过使用地址转换表执行地址转换的地址转换器。当通过解码CPU的指令而获得的地址是与缺省程序中的变化部分对应的地址时，地址翻译器将该地址翻译为其中设置有差分程序的地址。

15. 发明公开

EP3146433A1 MEMORY CONTROLLERS EMPLOYING MEMORY CAPACITY COMPRESSION, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS 审中-公开
标题翻译：与内存压缩和相关处理器的系统和方法存储器控制
公开(公告)号：EP3146433A1
公开(公告)日：2017-03-29
申请号：EP15726485.4
申请日：2015-05-20
申请人： Qualcomm Incorporated
发明人： HEDDES, Mattheus, Cornelis Antonius Adrianus , VAIDHYANATHAN, Natarajan , VERRILLI, Colin, Beaton
IPC分类号： G06F12/02
CPC分类号： G06F12/0802 , G06F12/023 , G06F2212/1016 , G06F2212/1056 , G06F2212/251 , G06F2212/305 , G06F2212/401 , G06F2212/608 , Y02D10/13
摘要： Aspects disclosed herein include memory controllers employing memory capacity compression, and related processor-based systems and methods. In certain aspects, compressed memory controllers are employed that can provide memory capacity compression. In some aspects, a line-based memory capacity compression scheme can be employed where additional translation of a physical address (PA) to a physical buffer address is performed to allow compressed data in a system memory at the physical buffer address for efficient compressed data storage. A translation lookaside buffer (TLB) may also be employed to store TLB entries comprising PA tags corresponding to a physical buffer address in the system memory to more efficiently perform the translation of the PA to the physical buffer address in the system memory. In certain aspects, a line-based memory capacity compression scheme, a page-based memory capacity compression scheme, or a hybrid line-page-based memory capacity compression scheme can be employed.
摘要翻译：在游离缺失方面盘包括存储器控制器用人存储器容量压缩，以及相关的基于处理器的系统和方法。在某些方面，压缩存储器控制器被采用并可以提供存储容量的压缩。在一些方面中，可以采用基于行的存储器容量的压缩方案，其中的物理地址（PA）到物理缓冲器地址的额外的转换被执行以允许在系统存储器的压缩数据在物理缓冲地址为有效的压缩数据存储，甲翻译旁视缓冲器（TLB）因此可以被用来存储TLB条目包括PA白天对应于系统中的存储器中的物理地址缓冲器更有效地执行PA的翻译系统中的存储器中的物理地址缓冲器。在某些方面，基于行的存储器容量的压缩方案，基于页面的存储器容量的压缩方案，或一个混合的基于行页存储器容量的压缩方案可以被使用。

16. 发明公开

EP3140749A1 IN-MEMORY LIGHTWEIGHT COHERENCY 有权
标题翻译： LEICHTE IN-SPEICHER-KOHÄRENZ
公开(公告)号：EP3140749A1
公开(公告)日：2017-03-15
申请号：EP15789090.6
申请日：2015-05-07
申请人： Micron Technology, Inc.
发明人： MURPHY, Richard C.
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G11C8/12 , G06F9/52 , G06F12/0284 , G06F12/0815 , G06F12/0817 , G06F12/0824 , G06F12/084 , G06F12/1072 , G06F2212/1032 , G06F2212/1048 , G06F2212/251 , G06F2212/3042 , G11C5/02 , G11C5/025
摘要： A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.
摘要翻译：系统包括多个主机处理器和被配置为用于主处理器的分布式共享存储器的多个HMC设备。 HMC设备包括多个集成电路存储器管芯，其包括布置在第二存储器管芯的顶部上的至少第一存储器管芯，并且映射存储器管芯的存储器的至少一部分以包括存储器连贯性的至少一部分目录; 以及包括至少一个存储器控制器的逻辑基准管芯，所述至少一个存储器控制器被配置为通过至少一个第二器件来管理对所述多个存储器管芯的存储器的三维（3D）存取），以及逻辑电路，被配置为确定存储在多个存储器管芯的存储器，传送关于对存储器的存取的信息，并且将所述存储器一致性信息包括在传送的信息中。

17. 发明公开

EP3077912A1 STEUERGERÄT FÜR EIN KRAFTFAHRZEUG 有权
标题翻译：控制装置的机动车辆
公开(公告)号：EP3077912A1
公开(公告)日：2016-10-12
申请号：EP14783847.8
申请日：2014-10-13
申请人： Robert Bosch GmbH
发明人： BIEWER, Alexander , THOSS, Dieter , GLADIGAU, Jens , HAUBELT, Christian
IPC分类号： G06F12/08 , G06F15/173
CPC分类号： G06F12/023 , G06F12/06 , G06F12/08 , G06F15/167 , G06F15/17325 , G06F2212/173 , G06F2212/251 , G06F2212/253
摘要： The invention relates to a control device (10) for a motor vehicle, wherein the control device (10) comprises at least two processor cores (110, 120, 130) and a global memory (300), wherein each processor core (110, 120, 130) comprises in each case a local memory (112), and wherein each processor core is set up to access only its own local memory and is set up to access neither the local memories in the other processor cores nor the global memory (300), wherein a coordination unit (200) is set up to read data from the global memory (300) of the control device (10) and to write said data to the local memories (112) in the individual processor cores (110, 120, 130) and to read data from the local memories (112) in the individual processor cores (110, 120, 130) and to write said data to the global memory (300) and/or to the local memories in the other processor cores.

18. 发明公开

EP2746953A4 DEMAND PAGING METHOD FOR MOBILE TERMINAL, CONTROLLER AND MOBILE TERMINAL 审中-公开
标题翻译：以需求为基础的寻呼的移动终端，控制及移动终端
公开(公告)号：EP2746953A4
公开(公告)日：2014-08-20
申请号：EP11859503
申请日：2011-08-15
申请人： SPREADTRUM COMM SHANGHAI CO
发明人： CHAI YIPENG , JIA MINGJUN , SHI YANSHAN
IPC分类号： G06F9/445 , G06F12/08 , G06F17/30 , H04L29/06 , H04L29/08 , H04W4/12 , H04W8/22
CPC分类号： G06F17/30153 , G06F12/08 , G06F17/3007 , G06F17/30129 , G06F2212/251 , G06F2212/253 , G06F2212/401 , H04L67/06 , H04L69/04

19. 发明公开

EP2761469A1 NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) AS A REPLACEMENT FOR TRADITIONAL MASS STORAGE 有权
标题翻译： NICHTFLÜCHTIGERDIREKTZUGRIFFSSPEICHER（NVRAM）ALS ERSATZFÜRHERKÖMMLICHENMASSENSPEICHER
公开(公告)号：EP2761469A1
公开(公告)日：2014-08-06
申请号：EP11873493.8
申请日：2011-09-30
申请人： Intel Corporation
发明人： PUTHIYEDATH, Leena, K. , FANNING, Blaise , OPFERMAN, Tony , CROSSLAND, James, B.
IPC分类号： G06F12/00 , G06F13/14 , G06F13/16
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。计算机系统包括执行软件的处理器和耦合到处理器的存储器。存储器的至少一部分包括由处理器进行字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）。该系统还包括耦合到NVRAM的存储器控制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

20. 发明公开

EP2721482A2 MEMORY MANAGEMENT MODEL AND INTERFACE FOR NEW APPLICATIONS 审中-公开
标题翻译：内存管理模型及界面为新的应用
公开(公告)号：EP2721482A2
公开(公告)日：2014-04-23
申请号：EP12802712.5
申请日：2012-06-18
申请人： Microsoft Corporation
发明人： SPRADLIN, Jeremiah C. , HUNT, Galen , JOHAR, Akshay , MAILLET, Steven
IPC分类号： G06F9/06 , G06F9/44 , G06F12/00
CPC分类号： G06F12/023 , G06F9/5016 , G06F12/0223 , G06F2212/1016 , G06F2212/1041 , G06F2212/251 , G06F2212/70
摘要： A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (API) that allows the application to specify more information about memory allocations that is helpful for managing memory later. The system also provides an ability to statically and/or dynamically analyze legacy applications to give applications that are not modified to work with the system some ability to participate in more effective memory management. The system provides application host changes to leverage the information provided by applications and to manage memory more effectively using the information and hooks into the application's use of memory. Thus, the system provides a new model for managing memory that improves application host behavior and allows applications to use computing resources more efficiently.

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