专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明公开

EP4250101A2 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-实审
公开(公告)号：EP4250101A2
公开(公告)日：2023-09-27
申请号：EP23191570.3
申请日：2011-09-30
申请人： Intel Corporation
发明人： Valentine, Robert C. , Corbal San Adrian, Jesus , Sans Espasa, Roger , Cavin, Robert D. , Toll, Bret L. , Duran Galan, Santiago , Wiedemeier, Jeffrey G. , Samudrala, Sridhar , Girkar, Milind Baburao , Grochowski, Edward Thomas , Hall, Jonathan Cannon , Bradford, Dennis R. , Ould-Ahmed-Vall, ElMoustapha , Abel, James C. , Charney, Mark , Abraham, Seth , Sair, Suleyman , Forsyth, Andrew Thomas , Yount, Charles , Wu, Lisa
IPC分类号： G06F9/30
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is to execute an instruction set. The instruction set includes a first instruction format, wherein the first instruction format includes a first plurality of templates, wherein the first instruction format has a plurality of fields including a base operation field, a data element width field, and a write mask field, wherein the first instruction format supports, through different values in the base operation field, specification of different vector operations, wherein each of the vector operations is to generate a destination vector operand including a plurality of data elements at different data element positions, wherein the first instruction format supports, through different values in the data element width field, specification of different data element widths, wherein the base operation field, the data element width field, and the write mask field may each store only one value on each occurrence of an instruction in the first instruction format in instruction streams. The processor includes a decode unit to decode the occurrences of the instructions in the first plurality of templates, including to: distinguish, for each of the occurrences, which one of the data element widths to use based on a value in the data element width field; and distinguish, for each of the occurrences, the data elements resulting from the occurrence's vector operation to be reflected in the destination vector operand's corresponding data element positions based on the write mask field's content and the data element width for the occurrence. Different values that may be stored in the write mask field distinguish different write mask registers, of a set of write mask registers, that are to store configurable write masks. The data element width for the occurrence distinguishes which of the data element positions of the destination vector operand correspond with which bits of the configurable write masks.

12. 发明公开

EP4053695A1 SYSTEMS, METHODS, AND APPARATUSES FOR DOT PRODUCTION OPERATIONS 审中-公开
公开(公告)号：EP4053695A1
公开(公告)日：2022-09-07
申请号：EP22169888.9
申请日：2017-07-01
申请人： INTEL Corporation
发明人： Valentine, Robert , Baum, Dan , Sperber, Zeev , Corbal, Jesus , Ould-Ahmed-Vall, ElMoustapha , Toll, Bret L. , Charney, Mark , Adelman, Menachem , Ziv, Barukh , Heinecke, Alexander , Rubanovich, Simon
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to matrix operations. For example, an apparatus comprises programmable configuration storage, decode circuitry and execution circuitry. The programmable configuration storage is to store configuration information for a first matrix, a second matrix, and a third matrix, the configuration information including a first value corresponding to a first number of rows for the first matrix, a second value corresponding to a second number of columns for the first matrix, a third value corresponding to a third number of rows for the second matrix, a fourth value corresponding to a fourth number of columns for the second matrix, a fifth value corresponding to a fifth number of rows for the third matrix, a sixth value corresponding to the sixth number of columns for the third matrix, and a start row value corresponding to a row of a corresponding matrix at which to restart execution of at least one of a plurality of matrix instructions. The decode circuitry is to decode the plurality of matrix instructions, including a single instruction to perform dot-product and accumulation, the single instruction having a first operand to specify a first register, a second operand to specify a second register, and a third operand to specify a third register. The execution circuitry is to perform one or more operations corresponding to the single instruction, including: performing dot-products on elements of the second matrix from the second register and elements of the third matrix from the third register to generate one or more resulting elements, and accumulating the one or more resulting elements into the first matrix in the first register.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式