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11. 发明公开

EP0385703A3 Keyboard interface control 失效
标题翻译：键盘接口控制
公开(公告)号：EP0385703A3
公开(公告)日：1992-06-24
申请号：EP90302044.4
申请日：1990-02-27
申请人： DATA GENERAL CORPORATION
发明人： Christensen, Mark E
IPC分类号： G06F3/023 , G06F13/38 , G06F13/42
CPC分类号： G06F3/023
摘要： In a system for handling data transfer between a synchronous keyboard (130) and a host processor (110), an asynchronous receiver/transmitter (220) is employed in conjunction with logic (120) for controlling the keyboard clock line (102) and data line (103) to permit the receipt of data from and the transmittal of data to the keyboard in a pseudo-synchronous manner.
摘要翻译：在用于处理同步键盘（130）和主处理器（110）之间的数据传输的系统中，异步接收器/发射器（220）与用于控制键盘时钟线（102）和数据的逻辑（120）结合使用线路（103）以允许以伪同步方式从数据接收数据和向键盘发送数据。

12. 发明公开

EP0483421A1 Method of operating a digital computer system 失效
标题翻译： Verfahren zum Betreiben eines Digitalrechnersystems。
公开(公告)号：EP0483421A1
公开(公告)日：1992-05-06
申请号：EP90311828.9
申请日：1990-10-29
申请人： DATA GENERAL CORPORATION
发明人： Farrell, John Michael , Gladstone, Philip John Steuart
IPC分类号： G06F9/46 , H04L12/58
CPC分类号： H04L51/066 , G06F9/542 , G06F9/546 , G06F17/2264
摘要： In a network communiction system passing messages between gateways (12) via a message handling system (15) the gateways (12) are interfaced specifically to their respective network access units (14) and are interfaced generically to the message handling system (15) using routines common to all gateways. Messages are sent in protocol data units including recipient addresses which do not identify recipient gateways as such; the gateways are used transparently. The data format is CCITT 1988 X400 standard with automatic conversion to and from this format at sending and receiving gateways plus automatic document conversion. Message handling involves waiting for many services and events. The invention allows calling routines to avoid pending while waiting for events and services. Service routines, including event watching and timer routines, schedule notifications on to queues and the main processing task runs notifications off the queues by calling a run routine.
摘要翻译：在通过消息处理系统（15）在网关（12）之间传递消息的网络通信系统中，网关（12）特别地与其各自的网络接入单元（14）进行接口，并且通常使用与消息处理系统（15）进行接口所有网关通用的例程。消息以协议数据单元发送，包括不识别接收网关的接收方地址; 网关透明地使用。数据格式为CCITT 1988 X400标准，在发送和接收网关以及自动文档转换时自动转换格式。消息处理涉及等待许多服务和事件。本发明允许呼叫例程在等待事件和服务的同时避免等待。服务程序，包括事件监视和定时器程序，对队列进行调度通知，主处理任务通过调用运行程序来运行队列中的通知。

13. 发明授权

EP0206816B1 Apparatus for increasing the switching speed of diodes 失效
标题翻译：增加二极管开关速度的装置
公开(公告)号：EP0206816B1
公开(公告)日：1992-05-06
申请号：EP86304902.9
申请日：1986-06-25
申请人： DATA GENERAL CORPORATION
发明人： Latham, Paul W.
IPC分类号： H03L7/08 , H03K17/74
CPC分类号： H03L7/0896

14. 发明公开

EP0382363A3 Method and apparatus for multiplexing sub-rate channels in a digital data communication system 失效
标题翻译：用于在数字数据通信系统中多路复用子速率信道的方法和装置
公开(公告)号：EP0382363A3
公开(公告)日：1991-11-27
申请号：EP90300619.5
申请日：1990-01-22
申请人： DATA GENERAL CORPORATION
发明人： Almond, Gary Robert , Storey, David W.
IPC分类号： H04J3/16
CPC分类号： H04Q11/0421 , H04J3/1647 , H04Q2213/13292 , H04Q2213/13367
摘要： To improve the efficiency of bandwidth usage over the CCITT I.463 standard, for switching systems having a granularity of better than 64 Kbps (e.g. 8 Kbps), in a system for performing rate adaptation for synchronized sub-rate channels in a manner geared to package sub-rate data in fragment size envelopes for integer multiples thereof), the width of a fragment is matched (ideally equal) to the granularity of the system's switch. This improves the efficiency of the rate adaptation process and maximizes the use of the system's switching and bandwidth capacity. In a system having m slots of bandwidth per frame, n fragments per slot and a switch granularity of x Kbps, x is less than 64 and each fragment is x Kbps wide.

15. 发明公开

EP0384620A3 High performance memory system 失效
标题翻译：高性能存储系统
公开(公告)号：EP0384620A3
公开(公告)日：1991-09-25
申请号：EP90301393.6
申请日：1990-02-09
申请人： DATA GENERAL CORPORATION
发明人： Burrer, Charlotte Amy , Krantz, Lawrence L.
IPC分类号： G06F12/06 , G06F11/00
CPC分类号： G06F11/1044 , G06F12/0607 , G11C7/00
摘要： An improved memory system for use in a data processing system has two memory banks (30,31) and corresponding error correction circuitry (34,35) associated with each. Data words of a block thereof are stored in the memory banks in an interleaved fashion wherein alternating words are stored in one bank and the intervening alternating words are stored in the other bank. During a WRITE operation the memory is controlled so that the first data word of a block stored in a memory bank uses a late write technique, and all subsequent data words thereof use an early write technique. During a READ operation, pairs of data words are read and checked for errors simultaneously, and are then supplied in a pipelined manner.

16. 发明授权

EP0212016B1 A system of graphical manipulation in a potentially windowed data display 失效
标题翻译：在可能的窗口数据显示中的图形处理系统
公开(公告)号：EP0212016B1
公开(公告)日：1990-10-31
申请号：EP85305716.4
申请日：1985-08-12
申请人： DATA GENERAL CORPORATION
发明人： Pilat, John , Keating, David , Colella, Wayne
IPC分类号： G09G1/00 , G09G1/16
CPC分类号： G09G5/14 , G09G2360/121

17. 发明公开

EP0384621A2 Data transfer operations between two asynchronous buses 失效
标题翻译： Bussen的Datenübertragungsbetriebzwischen zwei asynchronen。
公开(公告)号：EP0384621A2
公开(公告)日：1990-08-29
申请号：EP90301394.4
申请日：1990-02-09
申请人： DATA GENERAL CORPORATION
发明人： Gallo, Paul Samuel , Goodman, R.W.Benjamin , Krantz, Lawrence L. , McLoughlin, Kathleen A. , Wagner, Eric M.
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , G06F13/4031
摘要： A system for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously. When the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and transfers are made to the high speed bus at high speed when such bus is not busy. When the high speed bus requires access to the low speed bus, if the low speed bus is busy the requesting master on the high speed bus is temporarily placed in a pending status and is removed from its tenure on the high speed bus, so that the high speed bus is free to handle other requests. When the low speed bus is free, the highest priority pending requestor is provided access to the low speed bus on a priority basis over all then-current requestors.
摘要翻译：允许在独立和异步运行的高速总线和低速总线之间进行数据传输的系统。当低速总线需要访问高速总线时，确定后一个总线的忙碌状态，并且当这种总线不忙时，高速总线高速传输。当高速总线需要访问低速总线时，如果低速总线忙，则高速总线上的请求主机暂时处于挂起状态，并从高速总线上的任务中移除，以便高速巴士可以自由处理其他要求。当低速总线空闲时，优先级最高的请求者提供对所有当前请求者的优先级访问低速总线。

18. 发明公开

EP0309068A3 Digital data processing system 失效
标题翻译：数字数据处理系统
公开(公告)号：EP0309068A3
公开(公告)日：1990-08-16
申请号：EP88202398.9
申请日：1983-11-15
申请人： DATA GENERAL CORPORATION
发明人： Guyer, James M. , Keating, David Lee , Hummel, Mark Douglas , Epstein, David Ira , Normoyle, Kevin B. , Burns, Kenneth , Anderson, Walker , Kimmens, Harold R. , Veres, James Edward , Wallach, Steven Jeffrey
IPC分类号： G06F9/22
CPC分类号： G06F9/268 , G06F9/226 , G06F9/24 , G06F9/264 , G06F12/1027 , G06F2212/2515
摘要： The system comprises processor means (PU 106) for processing the data, a main memory (102) for storing the data and instructions for directing operations of the system, and a bus (MDA 110) for conducting the data and instructions between the memory and the processor means. The processor means comprise a CPU processor (CPUP 122) connected to the bus (MDA 110) for performing arithmetic and logic operations on the data. A microcode processor (IPD 114, US 116) is connected to the bus and is responsive to the instructions and the operations of the system for manipulating and providing sequences of microinstructions for controlling the operations of the system. The microcode processor (IPD 114, US 116) comprises means (IPD 114) connected to the bus (MDA 110) for receiving the instructions, means connected to other portions of the system for receiving information regarding the state of the operations of the system, a microcode memory for storing and providing the sequences of microinstructions, and microcode sequence control means responsive to the received instructions and to the state information for providing addresses to the microcode memory for selecting the sequences of microinstructions.
摘要翻译：该系统包括用于处理数据的处理器装置（PU 106），用于存储数据和用于指导系统操作的指令的主存储器（102），以及用于在存储器和存储器之间执行数据和指令的总线（MDA 110）处理器意味着。处理器装置包括连接到总线（MDA 110）的CPU处理器（CPUP 122），用于对数据执行算术和逻辑运算。微码处理器（IPD114，US116）连接到总线，并且响应系统的指令和操作以操纵和提供用于控制系统操作的微指令序列。微码处理器（IPD 114，US 116）包括连接到总线（MDA 110）用于接收指令的装置（IPD 114），连接到系统的其他部分以接收关于系统操作状态的信息的装置，用于存储和提供微指令序列的微码存储器，以及响应于所接收的指令和用于向微码存储器提供地址以选择微指令序列的状态信息的微码序列控制装置。

19. 发明公开

EP0223557A3 Display control in a data processing system 失效
标题翻译：数据处理系统中的显示控制
公开(公告)号：EP0223557A3
公开(公告)日：1989-04-05
申请号：EP86308825.8
申请日：1986-11-12
申请人： DATA GENERAL CORPORATION
发明人： O'Brien,Walter A. , Rich,David L. , Hurd,Charles C. , Pogue,Michael
IPC分类号： G09G1/00
CPC分类号： G09G5/14
摘要： In a distributed computer system, each CPU (101) accesses memory via an intelligent memory control unit (401) connected by a memory bus (404) to a local memory (102) and video memory (113) and by an interface bus to other memory control units (401) In the system. A video control unit (406) relieves the CPU (101) of much of the detailed work of modifying bit maps in the video memory (113). More specifically, in order to enhance the ability of the system to manage displays, especially in a technical graphics environment, where a single physical display supports a plurality of logical displays (windows), machine-language (graphics) instructions are provided which, in conjunction with logical display descriptors (forms) that describe each window, enable management and generation of display image data to be performed directly by the processing hardware of the digital computer system, minimizing the need for intervening software. Mechanisms are provided which gives the hardware the ability to defer complex protection and creation policies (faults) to operating system software. Data computed from the logical display descriptors may be encached, greatly enhancing the speed of consecutive operations on windows. Graceful creation is enhanced by permitting prosessing control to escape (trap) to software emulation handlers.

20. 发明公开

EP0206816A3 A charge pump for use in a phase-locked loop 失效
标题翻译：用于相位锁定环路的充电泵
公开(公告)号：EP0206816A3
公开(公告)日：1988-12-07
申请号：EP86304902
申请日：1986-06-25
申请人： DATA GENERAL CORPORATION
发明人： Latham, Paul W.
IPC分类号： H03L07/08 , H03K17/74
CPC分类号： H03L7/0896
摘要： A capacitor (3) provides the control voltage for a voltage-controlled oscillator (1) via a filter (15) and a phase comparator (2) provides UP and DN signals for changing the capacitor up and down from a single current source (14) via switches (13 and 12) when UP is true and DN is false and via switches (12 and 11) when DN is true and UP is false. The switches (10 and 11) are diodes switched rapidly by the smallest possible changes in the bias voltages therefor.

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