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91. 发明公开

EP0652593A2 Semiconductor integrated circuit device and production method thereof 失效
标题翻译： Integrierte Halbleiterschaltungsanordnung und Verfahren zu deren Herstellung。
公开(公告)号：EP0652593A2
公开(公告)日：1995-05-10
申请号：EP94117362.7
申请日：1994-11-03
申请人： HITACHI, LTD.
发明人： Yano, Kazuo , Sasaki, Yasuhiko
IPC分类号： H01L27/02 , H03K19/173
CPC分类号： H03K19/1735 , H01L27/0207 , H01L27/11807 , H01L2924/14 , H01L2924/00
摘要： The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal (22) is connected to a plurality of input terminals (19 to 21) through source-drain paths of active devices (M13 to M16) connected in the tree form, and gate electrodes of the active devices (M13 to M16) are connected to other input terminals (15 to 18). Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.
摘要翻译：半导体集成电路具有高性能，可以在低成本和短时间内生产。单元具有内部电路连接，使得输出端子（22）通过以树形形式连接的有源器件（M13至M16）的源极 - 漏极连接到多个输入端子（19至21），并且栅电极的有源器件（M13至M16）连接到其他输入端子（15至18）。具有相同内部电路连接的两个这样的单元，内部电路装置的相同配置和输入/输出端子的相同配置设置在同一芯片上，并且可以通过改变输入的应用形式来实现彼此不同的逻辑从单元外部到输入端子的信号。可以减少由CAD使用单元库设计的集成电路的芯片面积，并且可以实现高速电路操作。本发明对于提高ASIC，微处理器等的性能以及降低生产成本提供显着的效果。

92. 发明公开

EP0651513A1 Integrated circuit with bidirectional pin 失效
标题翻译： Integrierte Schaltung mit bidirektionnellem Anschlussstift。
公开(公告)号：EP0651513A1
公开(公告)日：1995-05-03
申请号：EP93830437.5
申请日：1993-10-29
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Monti, Marco
IPC分类号： H03K19/173
CPC分类号： H03K19/1732
摘要： An integrated circuit comprises at least one input terminal and at least one output terminal, respectively intended for receiving and transmitting digital and/or analog signals, being associated with discrete circuit portions of the integrated circuit which implement different logic functions. Advantageously, such terminals are coincident with a single pin (2), and a circuit means (10) is arranged within the integrated circuit (1) to detect the logic state of the pin (2).
摘要翻译：集成电路包括分别用于接收和发送数字和/或模拟信号的至少一个输入端子和至少一个输出端子，其与实现不同逻辑功能的集成电路的分立电路部分相关联。有利地，这种端子与单个引脚（2）重合，并且在集成电路（1）内布置电路装置（10）以检测引脚（2）的逻辑状态。

93. 发明公开

EP0647030A2 Integrated circuit devices 失效
标题翻译： Integrierte Schaltungsvorrichtungen。
公开(公告)号：EP0647030A2
公开(公告)日：1995-04-05
申请号：EP94115120.1
申请日：1994-09-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Landers, Robert J.
IPC分类号： H03K19/173 , H03K19/21
CPC分类号： H03K19/215 , H03K17/693 , H03K19/1736
摘要： A base cell device (10) includes a first transmission gate (12) configured as a multiplexer comprising an N-channel transistor (14) and a P-channel transistor (16). The base cell device (10) also includes a second transmission gate (18) configured as a multiplexer that comprises an N-channel transistor (20) and a P-channel transistor (22). The first transmission gate (12) and the second transmission gate (18) each receive a control signal C and an inverted control signal from an inverter (24). The first transmission gate (12) receives a first input signal (A) and the second transmission gate (18) receives a second input signal (B). The base cell device (10) generates a common output signal (O) from the first transmission gate (12) and the second transmission gate (18). The base cell device (10) is capable of performing all two input function operations.
摘要翻译：基站装置（10）包括被配置为包括N沟道晶体管（14）和P沟道晶体管（16）的多路复用器的第一传输门（12）。基站装置（10）还包括被配置为包括N沟道晶体管（20）和P沟道晶体管（22）的多路复用器的第二传输门（18）。第一传输门（12）和第二传输门（18）各自接收来自逆变器（24）的控制信号C和反相控制信号。第一传输门（12）接收第一输入信号（A），第二传输门（18）接收第二输入信号（B）。基站装置（10）从第一传输门（12）和第二传输门（18）产生公共输出信号（O）。基站装置（10）能够执行所有两个输入功能操作。

94. 发明公开

EP0621695A2 Integrated circuit with an active-level configurable pin and method therefor 失效
标题翻译：一种集成电路，包括一个可配置在有效电平的连接和相关联的方法。
公开(公告)号：EP0621695A2
公开(公告)日：1994-10-26
申请号：EP94104689.8
申请日：1994-03-24
申请人： MOTOROLA, INC.
发明人： Floyd, Jeffery A. , Matthews, Lloyd P.
IPC分类号： H03K19/173 , G06F1/22
CPC分类号： G06F1/22 , H03K19/1732
摘要： An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

95. 发明授权

EP0342590B1 Master slice type semiconductor integrated circuit 失效
标题翻译：安排主片类型的集成半导体电路。
公开(公告)号：EP0342590B1
公开(公告)日：1994-08-17
申请号：EP89108755.3
申请日：1989-05-16
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Tanaka, Yasunori Intellectual Property Division , Kobayashi, Teruo Intellectual Property Division , Ishibashi, Masahiro Intellectual Property Division
IPC分类号： H01L27/118 , H01L23/50 , H03K19/173
CPC分类号： H03K19/1735 , H01L23/5286 , H01L24/06 , H01L27/11898 , H01L2224/05554 , H01L2924/14 , H01L2924/00

96. 发明公开

EP0581461A2 Reprogrammable interconnect architecture using fewer storage cells than switches 失效
标题翻译：重新可编程互连体系结构使用较少的存储器单元作为开关。
公开(公告)号：EP0581461A2
公开(公告)日：1994-02-02
申请号：EP93305345.6
申请日：1993-07-08
申请人： APTIX CORPORATION
发明人： Srinivasan, Adi , Cai, Hong , Guo, Ta-Pen
IPC分类号： H03K19/173 , H03K17/693 , H03K19/177
CPC分类号： H03K19/1776 , H03K17/693 , H03K19/17704 , H03K19/17736
摘要： A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M
摘要翻译：第一用户重新可编程互连架构worin连接所选互连导体之间的N个开关元件提供。所述开关元件由M个有源存储元件，其中，M

97. 发明公开

EP0583371A4 OUTPUT LOGIC MACROCELL WITH ENHANCED FUNCTIONAL CAPABILITIES. 失效
标题翻译：输出和改进的功能可能性逻辑宏小区。
公开(公告)号：EP0583371A4
公开(公告)日：1993-11-16
申请号：EP92911860
申请日：1992-04-29
申请人： LATTICE SEMICONDUCTOR CORP
发明人： SHEN JU , CHAN ALBERT L , SHANKAR KAPIL , TSUI CYRUS
IPC分类号： H03K19/173 , H03K19/21 , H03K19/177
CPC分类号： H03K19/1736

98. 发明授权

EP0196084B1 Sequential logic circuit 失效
标题翻译：顺序逻辑电路
公开(公告)号：EP0196084B1
公开(公告)日：1993-06-16
申请号：EP86104150.7
申请日：1986-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shimizu, Hiroshi , Kaizuka, Masao
IPC分类号： H03K19/173
CPC分类号： H03K19/1733

99. 发明公开

EP0472650A4 PROGRAMMABLE LOGIC EXPANDER 失效
标题翻译：可编程逻辑扩展器
公开(公告)号：EP0472650A4
公开(公告)日：1993-02-24
申请号：EP90908864
申请日：1990-05-09
申请人： PLUS LOGIC, INC.
发明人： KAPLINSKY, CECIL, H.
IPC分类号： H03K19/173 , H03K19/177 , H03K19/00
CPC分类号： H03K19/17708

100. 发明公开

EP0482658A2 Semiconductor integrated circuit provided with emitter coupled logic input/output buffers 失效
标题翻译： Halbleiterintegrierte Schaltung mit ECL-Eingangs- Ausgangspuffern。
公开(公告)号：EP0482658A2
公开(公告)日：1992-04-29
申请号：EP91118227.7
申请日：1991-10-25
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Sakaue, Kenji
IPC分类号： H03K19/00 , H03K19/173 , G06F11/26
CPC分类号： H03K19/01812 , H03K19/0008
摘要： A semiconductor circuit (40) comprises a plurality of first Emitter Coupled Logic (ECL) input buffer (21₁...21 n ) and output buffers (22₁...22 n ), which are driven by a specific number (m ≧ 2) power supplies. Further it comprises a plurality of ECL test input buffers (23₁...23 n ) and test output buffers (24₁...24 n ) driven by a specific number of power supplies (m ≧ 2). The power supply lines (41a,41b,42a,42b) to the ECL input and output buffers are independent of the power supply lines of the test input and output buffers. Power is supplied to the test input and output buffers only during assembly of the integrated circut.
摘要翻译：半导体电路（40）包括由特定数量（m> / = 2）驱动的多个第一发射极耦合逻辑（ECL）输入缓冲器（211 ... 21n）和输出缓冲器（221 ... 22n））电源。此外，它包括由特定数量的电源（m> / = 2）驱动的多个ECL测试输入缓冲器（231 ... 23n）和测试输出缓冲器（241 ... 24n）。 ECL输入和输出缓冲器的电源线（41a，41b，42a，42b）独立于测试输入和输出缓冲器的电源线。仅在组合集成电路期间才将功率提供给测试输入和输出缓冲器。

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