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91. 发明公开

EP2002447A2 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN REMOTE BUFFER CIRCUITS 有权
标题翻译：不挥发存储器和方法在偏远缓冲器电路缓冲的数据冗余
公开(公告)号：EP2002447A2
公开(公告)日：2008-12-17
申请号：EP07758464.7
申请日：2007-03-13
申请人： Sandisk Corporation
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C16/04 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.

92. 发明授权

EP1089293B1 Memory test method and nonvolatile memory with low error masking probability 有权
标题翻译：存储器的测试方法和错误隐藏的非易失性存储器中，术语低概率
公开(公告)号：EP1089293B1
公开(公告)日：2008-12-10
申请号：EP99830617.9
申请日：1999-09-30
申请人： STMicroelectronics S.r.l.
发明人： Kumar, Promod
IPC分类号： G11C29/00
CPC分类号： G11C29/40
摘要： A nonvolatile memory device (10) has a signature code generator (14, 15, 17) generating a present signature code (Q) from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address (A) of a memory cell being addressed; in this case the output of the code generator (Q) is a function of data (D) read from the cell array (24), the previously calculated signature code (Q) and the address of the read data. The data are read in sequence, using an internal clock (CK) generated by an internal clock oscillator (11). In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code (Q) varies in dynamic way; at the end of memory scanning, the signature code (Q) is compared to an expected result.

93. 发明公开

EP1989562A1 DUAL-PATH, MULTIMODE SEQUENTIAL STORAGE ELEMENT 有权
标题翻译：连续多双向存储器元件
公开(公告)号：EP1989562A1
公开(公告)日：2008-11-12
申请号：EP07757747.6
申请日：2007-03-01
申请人： QUALCOMM Incorporated
发明人： GARG, Manish , HAMDAN, Fadi Adel
IPC分类号： G01R31/3185 , G11C29/00 , H03K3/037
CPC分类号： G01R31/318541 , G01R31/318572 , G11C29/1201 , G11C29/32
摘要： A dual-path, multimode sequential storage element (SSE) (10) is described herein. In one example, the dual-path, multimode SSE comprises first (14) and second (12) sequential storage elements, a data input, a data output, and a selector mechanism (16). The first and second sequential storage elements (14, 12) each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism (16) is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element (14) and the second sequential storage element comprises a master-slave storage element (12).

94. 发明授权

EP1205938B1 Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen 有权
标题翻译：一种集成电路，包括测试模式和方法，用于测试多个这样的集成电路的
公开(公告)号：EP1205938B1
公开(公告)日：2008-11-05
申请号：EP01122878.0
申请日：2001-09-24
申请人： Infineon Technologies AG
发明人： Dietrich, Stefan, Dr. , Heyne, Patrick , Marx, Thilo , Schoeniger, Sabine , Sommer, Michael , Hein, Thomas , Markert, Michael , Partsch, Torsten , Schroegmeier, Peter , Weis, Christian
IPC分类号： G11C29/00
CPC分类号： G11C29/003

95. 发明授权

EP1742228B1 Semiconductor memory with redundant rows and columns and a flexible redundancy architecture 有权
标题翻译：具有冗余行和列和灵活冗余体系结构的半导体存储器
公开(公告)号：EP1742228B1
公开(公告)日：2008-10-15
申请号：EP05292263.0
申请日：2005-10-26
申请人： Fujitsu Ltd.
发明人： Mori, Kaoru, c/o Fujitsu Limited , Okuyama, Yoshiaki, c/o Fujitsu Limited
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/838

96. 发明授权

EP1745489B1 COMPRESSION OF DATA TRACES FOR AN INTEGRATED CIRCUIT WITH MULTIPLE MEMORIES 无效
标题翻译：数据的压缩轨道为具有多个商店集成电路
公开(公告)号：EP1745489B1
公开(公告)日：2008-10-01
申请号：EP05748092.3
申请日：2005-05-11
申请人： Qualcomm, Incorporated
发明人： JOHN, Johnny K.
IPC分类号： G11C29/00 , G01R31/3185
CPC分类号： G06F11/348 , G01R31/3177 , G01R31/318505 , G06F11/3471 , G06F11/3476 , G11C29/40 , G11C29/56008 , G11C2029/0401
摘要： Techniques for performing data tracing in an integrated circuit with multiple embedded memories are described. A trace module within the integrated circuit forms packets of trace data for memory accesses of the multiple memories. The trace module includes multiple data capture units (one for each memory) and a trace stream generator. Each data capture unit includes a register, a comparator, an address compressor, a data compressor, and a packetizer. The register stores an address for a prior memory access of the associated memory. The comparator compares an address for a current memory access against the address stored in the register. The address and data compressors perform address and data compression, respectively, for the current memory access. The packetizer forms a packet of trace data for the current memory access. The trace stream generator generates a stream containing trace data packets from all data capture units.

97. 发明授权

EP1415305B1 DUTY-CYCLE-EFFICIENT SRAM CELL TEST 有权
标题翻译： - 关于向占空比的高效SRAM单元测试
公开(公告)号：EP1415305B1
公开(公告)日：2008-09-03
申请号：EP02787139.1
申请日：2002-07-11
申请人： International Business Machines Corporation , Compagnie IBM France
发明人： NELSON, Erik.A , PILO,Harold
IPC分类号： G11C29/00
CPC分类号： G11C29/28 , G11C29/34
摘要： A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

98. 发明授权

EP1061526B1 On chip data comparator with variable data and compare result compression 有权
标题翻译：内置的数据比较器，具有可变数据和比较结果压缩
公开(公告)号：EP1061526B1
公开(公告)日：2008-08-27
申请号：EP00106931.9
申请日：2000-03-31
申请人： Qimonda AG
发明人： Frankowsky, Gerd
IPC分类号： G11C29/00
CPC分类号： G11C29/36 , G11C29/40

99. 发明公开

EP1859452A4 MULTIPLY REDUNDANT RAID SYSTEM AND XOR-EFFICIENT IMPLEMENTATION 审中-公开
标题翻译：多核心冗余RAID系统和XD效率实施
公开(公告)号：EP1859452A4
公开(公告)日：2008-07-23
申请号：EP06738498
申请日：2006-03-15
申请人： TANDBERG DATA CORP
发明人： DICKSON LAWRENCE JOHN
IPC分类号： G11C29/00
CPC分类号： H03M13/158 , G06F11/1076 , H03M13/1515 , H03M13/1575 , H03M13/616
摘要： An improved and extended Reed-Solomon-like method providing a redundancy of m≥3 is disclosed. A general expression of the codes and a systematic criterion for proving code correctness and finding decoding algorithms are described. Example codes for m=3, 4 and 5 based on primitive elements of a finite field of dimension N=8, 16 or 32 are given. A Homer's method and accumulator are described for XOR-efficient (15, 17) evaluation of polynomials with variable vector coefficients and a sparse square matrix abscissa. A power balancing technique is described to further improve XOR-efficiency of the algorithms. A tower coordinate technique to efficiently carry out finite field multiplication or inversion for large dimension N forms a basis for one decoding method. Another decoding method uses Schur expressions and a one-dimensional table of α powers to efficiently calculate the inverses of encoding matrix submatrices.
摘要翻译：公开了提供m≥3的冗余的改进和扩展的Reed-Solomon-like方法。描述了代码的一般表达和用于验证代码正确性和找到解码算法的系统标准。给出了基于维数N = 8,16或32的有限域的基本元素的m = 3,4和5的示例代码。荷马方法和累加器被描述为XOR高效（15,17）评估具有可变矢量系数和稀疏方形矩阵横坐标的多项式。描述了功率平衡技术以进一步提高算法的异或效率。对于大尺寸N有效地执行有限域乘法或反演的塔坐标技术形成了一种解码方法的基础。另一种解码方法使用Schur表达式和α权力的一维表来高效地计算编码矩阵子矩阵的逆矩阵。

100. 发明公开

EP1938333A2 ERROR DETECTION AND CORRECTION IN DATA TRANSMISSION PACKETS 审中-公开
标题翻译：数据传输包中的错误检测和校正
公开(公告)号：EP1938333A2
公开(公告)日：2008-07-02
申请号：EP06825641.1
申请日：2006-10-06
申请人： Newport Media, Inc. , XU, Bin , YOUSEF, Nabil
发明人： XU, Bin , YOUSEF, Nabil
IPC分类号： G11C29/00 , H04N7/26
CPC分类号： H03M13/1515 , H03M13/09 , H03M13/154 , H03M13/2906 , H03M13/2915 , H03M13/293 , H03M13/2948 , H03M13/373 , H03M13/6541
摘要： A system and method (700) of using recursive cyclic redundancy check (CRC) + forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder + FEC to achieve better coding gain.The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme (701) for implementing the recursive CRC/RS +FEC in very large scale integrated circuit chip (VLSI) hardware.
摘要翻译：一种使用递归循环冗余校验（CRC）+前向纠错（FEC）来增强DVB-H接收机的信道编码增益并且使用物理（PHY）Reed-Solomon（RS）解码器的系统和方法（700） + FEC来实现更好的编码增益。该系统和方法利用双模式RS解码器（擦除模式和错误模式）进行FEC解码。 PHY RS用于为FEC提供更小的粒度。该系统包括用于在超大规模集成电路芯片（VLSI）硬件中实现递归CRC / RS + FEC的高速缓冲存储器管理方案（701）。

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