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91. 发明公开

EP0993046A2 Verfahren zum Einbauen von Schutz-Bauelementen in aus Standardzellen aufgebauten integrierten Schaltungen 审中-公开
标题翻译：在由标准单元的集成电路的安装保护元件的方法
公开(公告)号：EP0993046A2
公开(公告)日：2000-04-12
申请号：EP99118270.0
申请日：1999-09-14
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Thiele, Jörg, Dr. , Hübl, Markus
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L27/11803 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： Die Erfindung betrifft ein Verfahren zum Einbauen von Schutz-Bauelementen in aus Standardzellen aufgebauten integrierten Schaltungen, bei dem

(a) in den Standardzellen der für wenigstens ein Schutz-Bauelement benötigte Platz reserviert wird,
(b) nach Verdrahtung der Standardzellen diejenigen Standardzellen bestimmt werden, die ein Schutz-Bauelement erfordern, und
(c) in die so bestimmten Standardzellen die Schutz-Bauelemente eingesetzt werden.
摘要翻译：本发明涉及一种安装在由标准单元的集成电路的保护部件的方法，其中（a）在所需要的至少一个保护部件空间中的标准单元，（b）关于标准单元的布线，这些标准单元被确定被保留，这需要在所谓一定的标准细胞有保护部件，和（c）中，使用的保护装置。

92. 发明公开

EP0855742A1 Semiconductor integrated circuit device produced from master slice and having operation mode easily changeable after selection on master slice 失效
标题翻译：自定义的半导体集成电路根据客户特定的电路的选择，其操作方式是稍微改变
公开(公告)号：EP0855742A1
公开(公告)日：1998-07-29
申请号：EP98101071.3
申请日：1998-01-22
申请人： NEC CORPORATION
发明人： Ohashi, Masayuki
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/11803 , H01L27/0207 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor integrated circuit device is responsive to a potential level applied to a signal pad (21) connected to a mode changer (18), and the mode changer causes a mode selector (17) to change a control signal (MOD) between a first level indicative of a certain combination of sub-circuits (12a-12d) of a main circuit selected before separation of the semiconductor chip (10) from a master slice (11) and a second level indicative of another combination of the sub-circuits not selected by a customer; when the manufacturer evaluates the semiconductor integrated circuit device, the manufacturer changes the potential level at the signal pad (21), and carries out a test for the certain combination and another combination; when the semiconductor chip (10) is sealed in a package (40), the signal pad is electrically isolated from a source of potential level, and the control signal is fixed to the first level.
摘要翻译：一种半导体集成电路装置，是响应于施加到连接到模式改变器（18）的信号垫（21）的电势电平，并且模式改变引起的模式选择器（17）到第一之间改变的控制信号（MOD）表示的主电路的子电路（12A-12D）的特定组合的电平从主片层（11）和一个第二电平指示所述子电路的另一组合的不与半导体芯片（10）的分离之前选择由顾客选定的; 当制造商评估半导体集成电路器件，制造商改变在信号焊盘（21）的电位电平，并执行用于某些组合和另一组合的测试; 当半导体芯片（10）在包装（40）是密封的，所述信号焊盘是由电势电平的源极电隔离，并且该控制信号被固定为第一电平。

93. 发明公开

EP0657937A1 An improved gate array architecture and layout for deep space applications 失效
标题翻译： Verbesserte Gate-Arroy-Architektur und AnordnungfürWeltraumanwendungen。
公开(公告)号：EP0657937A1
公开(公告)日：1995-06-14
申请号：EP94309035.7
申请日：1994-12-05
申请人： UNITED TECHNOLOGIES CORPORATION
发明人： Gardner, Harry N. , Gregory, Charles R. , Garvie, Douglas W.
IPC分类号： H01L27/118
CPC分类号： H01L27/11803
摘要： The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.
摘要翻译：本发明教导了一种集成电路（“IC”）门阵列，其具有改进的可靠性和对来自电磁辐射，光子能量和带电粒子的深空干扰的增强的抗扰性。在本发明的一个实施例中，门阵列包括第一和第二逻辑分量以及第一和第二隔离晶体管。第一隔离晶体管和第二隔离晶体管都包括输入端，具有电压电位的偏置总线，以及用于将偏置总线与输入电耦合的电触头。此外，门阵列包括用于增加门阵列对带电粒子，电磁辐射和光子能量的免疫力的冗余耦合。

94. 发明公开

EP0641025A1 Integrated circuit gate arrays 失效
标题翻译：门阵列整合器Schaltung。
公开(公告)号：EP0641025A1
公开(公告)日：1995-03-01
申请号：EP94305217.5
申请日：1994-07-15
申请人： ASPEC TECHNOLOGY INC
发明人： Yin, Patrick
IPC分类号： H01L27/118
CPC分类号： H01L27/11803 , H01L27/11807
摘要： A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.
摘要翻译：公开了一种门阵列架构，其利用比现有技术显着更少的硅面积。核心单元包括四晶体管布置，其中衬底抽头位于晶体管对附近。这提供了比现有技术中更“对称”的单元阵列。通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。此外，门阵列架构镜像成对的晶体管列以允许在列对之间共享衬底抽头。此镜像功能进一步降低了路由复杂度。

95. 发明授权

EP0264334B1 Synchronous array logic circuit 失效
标题翻译：同步阵列的逻辑电路。
公开(公告)号：EP0264334B1
公开(公告)日：1994-12-28
申请号：EP87402305.4
申请日：1987-10-16
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Rees, David B. , Bahra, Avi Singh , Cooke, David , Gill, Jaspal Singh , Glennon, Michael Joseph , Hesketh, John Alban , McVicar, Alison C. , Ross, Nigel Keir , Turnbull, Keith Warwick , Warren, Robert G.
IPC分类号： H03K19/096 , H03K19/173
CPC分类号： H01L27/11803 , H03K19/096 , H03K19/1738

96. 发明公开

EP0421168A3 Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region 失效
标题翻译：具有金属互连层的半导体存储器作为字线并且在存储器区域外部连接
公开(公告)号：EP0421168A3
公开(公告)日：1994-07-13
申请号：EP90117656.0
申请日：1990-09-13
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Takase, Shinsuke, c/o Intellectual Property Div. , Hashimoto, Hisashi, c/o Intellectual Property Div. , Tanaka, Yutaka, c/o Intellectual Property Div.
IPC分类号： H01L27/118 , G11C8/00 , G11C5/06 , H01L27/112
CPC分类号： H01L27/112 , H01L27/11803 , Y10S257/903
摘要： Memory cells (21), which serve as basic cells, are arranged in a matrix pattern. The memory cells (21) are each provided with a word line (W′) which is integral with the gate electrode of a switch element (SW) and which is formed of polysilicon. A metallic interconnection layer (M) is arranged above the word line (W′) and is applied with substantially the same potential as the word line (W′). The metallic interconnection layer (M) and the word line (W′) are connected together via through-holes (23A). The through-holes (23A) are formed in through-hole cells (23), which also serve as basic cells. The through-hole cells (23) and the memory cells (21) are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.
摘要翻译：用作基本单元的存储单元（21）以矩阵图案排列。存储单元（21）各自设置有与开关元件（SW）的栅电极成一体并由多晶硅形成的字线（W min）。金属互连层（M）布置在字线上方（W min），并施加与字线（W min）基本相同的电位。金属互连层（M）和字线（W min）通过通孔（23A）连接在一起。通孔（23A）形成在也用作基本电池的通孔电池（23）中。通孔单元（23）和存储单元（21）布置成使得前者的行数和后者的行数之比为1至至少2。

97. 发明公开

EP0421857A1 Circuit électronique intermédiaire prédiffusé 失效
标题翻译： Periphere elektronische Schaltung nach Kundenwunsch。
公开(公告)号：EP0421857A1
公开(公告)日：1991-04-10
申请号：EP90402707.5
申请日：1990-10-01
申请人： THOMSON COMPOSANTS MICROONDES
发明人： Gobbi, José Maria , Le Berre, Louis
IPC分类号： H01L27/118
CPC分类号： H01L27/118 , H01L27/11803
摘要： L'invention concerne un circuit d'interface, implanté à la périphérie d'un circuit intégré prédiffusé. Il est destiné à adapter les niveaux d'entrée et de sortie vers un circuit extérieur, entre circuits de technologies différentes : BFL, ECL, CMOS...
En vue de rendre cet interface polyvalent, soit en entrée soit en sortie, et adapté à la technologie du circuit extérieur, l'interface comprend une pluralité de composants (9 à 12) et de fonctions (1 à 8) : au moment de la personnalisation du circuit prédiffusé, les composants et fonctions choisis sont métallisés pour les transformer en un interface d'entrée, ou de sortie ou en buffer interne, qui se trouve positionné au meilleur emplacement, avec des jonctions courtes.
Application aux circuits prédiffusés personnalisables.
摘要翻译：本发明涉及一种植入半定制集成电路周边的接口电路。用于将输入和输出电平适配到不同技术的电路之间的外部电路：BFL，ECL，CMOS等。为了使该接口在输入或输出端上多用途，并适用于外部电路的技术，接口包括多个组件（9至12）和功能（1至8）：当定制半定制电路时，所选择的组件和功能被金属化以将它们转换成输入接口或输出接口，或位于最佳位置的内部缓冲器，具有短路口。应用于可定制的半定制电路。

98. 发明公开

EP0421168A2 Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region 失效
标题翻译：半导体存储器与由相同的电位的字线和与该存储区域外部连接的金属接合层。
公开(公告)号：EP0421168A2
公开(公告)日：1991-04-10
申请号：EP90117656.0
申请日：1990-09-13
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Takase, Shinsuke, c/o Intellectual Property Div. , Hashimoto, Hisashi, c/o Intellectual Property Div. , Tanaka, Yutaka, c/o Intellectual Property Div.
IPC分类号： H01L27/118 , G11C8/00 , G11C5/06 , H01L27/112
CPC分类号： H01L27/112 , H01L27/11803 , Y10S257/903
摘要： Memory cells (21), which serve as basic cells, are arranged in a matrix pattern. The memory cells (21) are each provided with a word line (W′) which is integral with the gate electrode of a switch element (SW) and which is formed of polysilicon. A metallic interconnection layer (M) is arranged above the word line (W′) and is applied with substantially the same potential as the word line (W′). The metallic interconnection layer (M) and the word line (W′) are connected together via through-holes (23A). The through-holes (23A) are formed in through-hole cells (23), which also serve as basic cells. The through-hole cells (23) and the memory cells (21) are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.
摘要翻译：存储器单元（21），其用作基本单元，被布置成矩阵图案。存储器单元（21）均设置有一个字线（W分钟），所有这些是与开关元件（SW）的栅极电极和积分的所有其上形成多晶硅构成。的金属互连层（M）的字线（W分钟）以上被布置和被施加有基本上相同的电位作为字线（W分钟）。该金属互连层（M）和字线（W分钟）经由通孔（23A）连接在一起。通孔（23A）形成在贯通孔的细胞（23），其因此用作基本单元。贯通孔的细胞（23）和存储单元（21）被布置检查做的前者和后者的行数的行数是在一个的至少两个的比率。

99. 发明公开

EP0264334A3 Synchronous array logic circuit 失效
标题翻译：同步阵列逻辑电路与系统
公开(公告)号：EP0264334A3
公开(公告)日：1991-04-10
申请号：EP87402305.4
申请日：1987-10-16
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Rees, David B. , Bahra, Avi Singh , Cooke, David , Gill, Jaspal Singh , Glennon, Michael Joseph , Hesketh, John Alban , McVicar, Alison C. , Ross, Nigel Keir , Turnbull, Keith Warwick , Warren, Robert G.
IPC分类号： H03K19/096 , H03K19/173
CPC分类号： H01L27/11803 , H03K19/096 , H03K19/1738
摘要： Synchronous array logic circuitry and a system for automatically laying out such circuitry for the fabrication of integrated circuits are described. The synchronous array logic circuitry includes as many cells (10, 20...) as necessary to perform the desired functions with each cell including a transistor array (12) for evaluating a Boolean function and supplying the result to a storage element (18) through a multiplexer (15). The storage element (18) latches the output signal and supplies it to other transistor arrays and/or other cells. The transistor array (12) includes serially connected transistors for performing AND functions and parallel connected transistors for performing OR functions. The multiplexer (15) operates under control of a test signal to configure the storage elements serially, thereby enabling complete testability of all cells (10, 20). Our system includes a method for automatically laying out such circuitry. The method includes steps of arranging the storage elements (18) in a desired order, assigning transistors within a given cell to positions along a first axis, assigning transistors within the cell to a position along a perpendicular axis, and laying out an interconnecting diffusion path. Once all cells are specified, the cells may be interconnected in a desired manner.

100. 发明公开

EP0376291A3 Semiconductor integrated circuit 失效
公开(公告)号：EP0376291A3
公开(公告)日：1991-01-30
申请号：EP89124039.2
申请日：1989-12-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakata, Shigeharu Intellectual Property Division , Andoh, Kazumasa Intellectual Property Division
IPC分类号： H01L27/02 , H01L27/118 , H01L23/50 , H01L23/528
CPC分类号： H01L23/5286 , H01L23/528 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit comprises a plurality of bus line means (D0 to D7) for transferring data, a plurality of bus line driving means (34 to 39), connected to the bus line means (D0 to D7) and including one or more FETs, for determining a logical level of the bus line means (D0 to D7), and a ground potential wire (41) connected to the bus line driving means (34 to 39) and arranged parallel to the bus line means (D0 to D7).

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