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91. 发明授权

EP0542546B1 Substrate to heatsink interface apparatus and method 失效
标题翻译：基板和散热片和方法之间的接口装置。
公开(公告)号：EP0542546B1
公开(公告)日：1995-11-08
申请号：EP92310343.6
申请日：1992-11-12
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Samarov, Victor M.
IPC分类号： H01L23/40 , H01L23/373
CPC分类号： H01L23/367 , H01L21/4882 , H01L23/3736 , H01L2924/0002 , Y10T29/49359 , H01L2924/00

92. 发明授权

EP0375105B1 Memory apparatus for multiple processor systems 失效
标题翻译：用于多处理器系统的存储器设备。
公开(公告)号：EP0375105B1
公开(公告)日：1995-10-25
申请号：EP89306724.9
申请日：1989-07-03
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Umina, Leonard John , Anselmo, Robert Anthony
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/005

93. 发明授权

EP0306252B1 Fault tolerant computer system input/output interface 失效
标题翻译：一个容错计算机系统的输入/输出接口。
公开(公告)号：EP0306252B1
公开(公告)日：1995-09-27
申请号：EP88307990.7
申请日：1988-08-30
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Bruckert, William F. , Bissett, Thomas D. , Norcross, Mitchell O. , Ward, Kenneth A.
IPC分类号： G06F11/00 , G06F11/16 , G06F13/00
CPC分类号： G06F11/165 , G06F11/004 , G06F11/0724 , G06F11/076 , G06F11/08 , G06F11/10 , G06F11/1044 , G06F11/1658 , G06F11/1666 , G06F11/2017 , G06F11/2205 , G06F11/2236 , G06F2201/845
摘要： A fault tolerant computer system includes a fault tolerant data processing module which has means for detecting and correcting errors in the operation of the data processing module to maintain a high degree of data integrity. Data transmission control devices control the transmission of all data to the fault tolerant data processing module and the receipt of all data into the fault tolerant data processing module. Input/output terminals are coupled to the data transmission control means for receiving and transmitting data. A non-fault tolerant input/output module is coupled to transmit the data to the input/output terminals of the fault tolerant data processing module. This module includes a read device for transferring data to the fault tolerant computing system in response to requests from the data transmission control devices, and a firewell for preventing the non-fault tolerant input/output module from initiating transfers of data to the fault tolerant data processing module.

94. 发明授权

EP0405968B1 Clock recovery for serial data communications system 失效
标题翻译：时钟恢复的串行数据通信系统。
公开(公告)号：EP0405968B1
公开(公告)日：1995-09-13
申请号：EP90307072.0
申请日：1990-06-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Davies, David C. , Vonada, Donald G.
IPC分类号： H04L7/033 , H03L7/06
CPC分类号： H04L7/033

95. 发明授权

EP0352883B1 Network topology control method and apparatus 失效
标题翻译：的方法和装置的网络拓扑的控制。
公开(公告)号：EP0352883B1
公开(公告)日：1995-09-13
申请号：EP89304502.1
申请日：1989-05-04
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Hutchison, Jerry , Yang, Henry , Hawe, William
IPC分类号： H04L12/42 , H04L12/24
CPC分类号： H04L41/12 , H04L12/42

96. 发明授权

EP0352081B1 Efficient protocol for communicating between asynchronous devices 失效
标题翻译：强大的协议异步设备之间的传输。
公开(公告)号：EP0352081B1
公开(公告)日：1995-08-16
申请号：EP89307289.2
申请日：1989-07-19
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Bowhill, William J. , Dickson, Robert , Durdan, Hugh W.
IPC分类号： G06F13/42
CPC分类号： G06F13/4213

97. 发明授权

EP0306209B1 Dual rail processors with error checking at single rail interfaces 失效
标题翻译：双轨处理器与单栏界面上的错误检查。
公开(公告)号：EP0306209B1
公开(公告)日：1995-06-21
申请号：EP88307854.5
申请日：1988-08-24
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Bruckert, William F. , Bissett, Thomas D. , Riegelhaupt, Norbert H.
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G06F11/1633 , G06F11/10 , G06F11/165

98. 发明授权

EP0259224B1 Method for performance evaluation of a data processor system 失效
标题翻译：用于估计的数据处理器系统的性能的方法。
公开(公告)号：EP0259224B1
公开(公告)日：1995-05-10
申请号：EP87401948.2
申请日：1987-08-31
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Chinnaswamy, Ackanaickenpalayam V. , Wilk, Stanley A. , Torrey, James H, Jr.
IPC分类号： G06F11/34
CPC分类号： G06F11/34 , G06F2201/81 , Y10S706/916
摘要： A method for evaluating the performance of a data processor system includes data collection, analysis, and report generation. The data collection involves the periodic selection of a number of metrics, which are measurable values in the data processing system, and system parameters, which are system values that can be adjusted. The analysis involves the application of certain rules comparing metrics and parameters to corrersponding thresholds. The report generation includes the display of recommendations to be taken when certain rules have triggered a certain number of times, and, if desired, the presentation of displays of certain work load characteristics of either the data processor system by itself or of a network of such data processor system.

99. 发明授权

EP0332662B1 BYTE WRITE ERROR CODE METHOD AND APPARATUS 失效
标题翻译： BYTE写错误代码方法和设备
公开(公告)号：EP0332662B1
公开(公告)日：1995-03-01
申请号：EP88904317.0
申请日：1988-04-29
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： SMELSER, Donald, W. , STEGEMAN, James, C. , CHISVIN, Lawrence, A.
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F11/1056 , H03M13/00 , H03M13/13
摘要： A method and apparatus for error detection is disclosed. A data word (54) and its check bits (56) are read from memory (16), and new check bits (60) are generated from the data word (54) read. A logical operation (62) is performed between the new check bits (60) and the check bits (56) read from memory (16) to generate a syndrome (64). The syndrome (64) is decoded to detect the presence or absence of an uncorrectable error. If an uncorrectable error is detected, a logical operation (120) is performed between the new check bits (56) and a byte write error code (116) to generate a third set of check bits, which are then written into memory (16) along with the data word.
摘要翻译：公开了一种用于错误检测的方法和设备。从存储器（16）读取数据字（54）及其校验位（56），并且从读取的数据字（54）产生新的校验位（60）。在新的校验位（60）和从存储器（16）读取的校验位（56）之间执行逻辑运算（62）以产生校正子（64）。综合征（64）被解码以检测是否存在不可纠正的错误。如果检测到不可纠正的错误，则在新的校验位（56）和字节写入错误码（116）之间执行逻辑操作（120）以生成第三组校验位，然后将其写入存储器（16）以及数据字。

100. 发明公开

EP0637071A2 Planarization process for IC trench isolation using oxidised polysilicon filler 失效
标题翻译：一种用于平坦化用的多晶硅填充料的集成电路中形成隔离沟槽的方法。
公开(公告)号：EP0637071A2
公开(公告)日：1995-02-01
申请号：EP94305322.3
申请日：1994-07-20
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Nasr, Andre Ilyas, , Cooperman, Steven Scott
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/76
CPC分类号： H01L21/763
摘要： Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches (20-23) and active areas (31-34) on a semiconductor substrate (10) are conformally coated with a layer (15) of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks (30) in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.
摘要翻译：平面化的半导体基板包括形成在表面上平坦有源区台面和沟槽（31,32,33,34），沉积保形电介质，或电介质前体，在所述面（15）在形成沟槽上述凹部，以及沉积层的硅（25）移到该。在Si与光致抗蚀剂图案化以形成抗蚀剂在凹陷块（30）中，Si蚀刻到离开合成块下方段中，Si退火以将其转换为氧化物，和抛光至有源区的顶部的面，得到一个平坦的表面。这样一种被如对上述Si衬底，以将电介质为二氧化硅的方法，多晶Si层，然后沉积具有厚度的凹部的一半的深度，然后平面化如上述进行。

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