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1. 发明授权

EP2235824B1 HIGH-FREQUENCY COUNTER 有权
标题翻译： HIGH FREQUENCY COUNTER
公开(公告)号：EP2235824B1
公开(公告)日：2011-06-15
申请号：EP08737764.4
申请日：2008-04-08
申请人： NXP B.V.
发明人： VAN DE BEEK, Remco, C.H.
IPC分类号： H03K5/135 , H03L7/091 , H03L7/113 , H03K23/58
CPC分类号： H03K5/135 , H03K23/588 , H03L7/113 , H03L7/18 , H03L2207/50
摘要： The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.

2. 发明公开

EP1675266A2 An improved area efficient programmable frequency divider 有权
标题翻译： Flächeneffizienterprogrammierbarer Frequenzteiler
公开(公告)号：EP1675266A2
公开(公告)日：2006-06-28
申请号：EP05107860.8
申请日：2005-08-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Chatterjee, Kallol , Jain, Deependra
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/665 , H03K21/40 , H03K23/667
摘要： A programmable high-speed frequency divider, in which stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified to reduce the area and circuit complexity. A start-up circuitry has been introduced within the said frequency-divider to ensure that the frequency-divider will never go into false state.
摘要翻译：一种可编程高速分频器，其中能够以可编程分频比编程的用于形成分频器的级被简化以减小面积和电路复杂度。在所述分频器内引入了启动电路，以确保分频器永远不会进入假状态。

3. 发明公开

EP0592260A1 Circuit de comptage pour division de fréquence, et synthétiseur équipé d'un tel circuit 失效
标题翻译： ZählschaltungfürFrequenzteilung und Synthetisierer mit einer derartigen Schaltung。
公开(公告)号：EP0592260A1
公开(公告)日：1994-04-13
申请号：EP93402155.1
申请日：1993-09-03
申请人： THOMSON-CSF
发明人： Boutigny, Pierre-Henri
IPC分类号： H03K23/50 , H03K23/00 , H03K23/58 , H03K23/66
CPC分类号： H03K23/62 , H03L7/183
摘要： L'invention concerne les circuits de comptage utilisés pour effectuer une division de fréquence.
Dans les circuits de comptage classiques la période minimale des impulsions à compter (I) doit être supérieure à la somme des temps de traitement de tous les additionneurs (A1-A5) en série dans le circuit. L'introduction de registres tampons (R1-R5) entre les additionneurs permet, par à la mise en mémoire des signaux de retenue, d'augmenter fortement la fréquence de comptage puisque la période minimale se réduit alors à la somme des temps de travail d'un additionneur et d'un registre.
Application, en particulier, aux circuits de comptage employés dans les synthétiseurs de fréquence.
摘要翻译：本发明涉及用于执行频率分割的计数电路。在常规计数电路中，要计数的脉冲的最小周期（I）必须大于电路中串联的所有加法器（A1-A5）的处理时间之和。在加法器之间引入缓冲寄存器（R1-R5）使得可以通过存储器进位信号来增加计数频率，因为最小周期然后减小到加法器的工作时间之和和一个登记册。尤其适用于频率合成器中使用的计数电路。

4. 发明公开

EP4331118A1 SYNCHRONOUS DIVIDER BASED ON CASCADED RETIMING 审中-实审
公开(公告)号：EP4331118A1
公开(公告)日：2024-03-06
申请号：EP22725419.0
申请日：2022-04-25
申请人： International Business Machines Corporation
发明人： KOSSEL, Marcel , FRANCESE, Pier Andrea , PRATHAPAN, Mridula , YONAR, Abdullah Serdar
IPC分类号： H03K21/10 , H03K23/58

5. 发明公开

EP2235824A2 HIGH-FREQUENCY COUNTER 有权
标题翻译：高频计数器
公开(公告)号：EP2235824A2
公开(公告)日：2010-10-06
申请号：EP08737764.4
申请日：2008-04-08
申请人： NXP B.V.
发明人： VAN DE BEEK, Remco, C.H.
IPC分类号： H03K5/135 , H03L7/091 , H03L7/113 , H03K23/58
CPC分类号： H03K5/135 , H03K23/588 , H03L7/113 , H03L7/18 , H03L2207/50
摘要： The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.
摘要翻译：计数器电路和控制这种计数器电路的方法技术领域本发明涉及计数器电路和控制这种计数器电路的方法，其中第一计数部分根据状态周期进行计数，并且第二计数部分由第一计数部分计时。在第一计数部分完成状态循环之前，通过控制第二计数部分改变其状态来引入至少一个无效计数状态; 然后检测并校正至少一个无效计数状态。因此，计数器中引入了一些冗余，可用于检测和纠正计数器状态的不完整切换。

6. 发明公开

EP0115004A1 Ripple counter circuit having reduced propagation delay 有权
标题翻译：异步计数器电路具有减少的运行时间。
公开(公告)号：EP0115004A1
公开(公告)日：1984-08-08
申请号：EP83112704.8
申请日：1983-12-16
申请人： MOTOROLA, INC.
发明人： Akram, Faheem M.
IPC分类号： H03K23/58
CPC分类号： H03K23/58
摘要： A ripple counter circuit (24) is provided that reduces propagation delay inherent in flip-flops, and therefore, reduces the current required. A first flip-flop (26) has a clock input ( CLK ) responsive to a clock signal and a D input connected to a Q output. A second flip-flop (30) has a clock input ( CLK ) ANDed to a O 1 output of the first flip-flop (26) and the clock signal. A propagation delay normally associated with the first flip-flop (26) is eliminated from the O 1 output of the first flip-flop (26).

7. 发明公开

EP0030857A2 Programmable counter circuit 失效
标题翻译： ProgrammierbareZählschaltung。
公开(公告)号：EP0030857A2
公开(公告)日：1981-06-24
申请号：EP80304498.1
申请日：1980-12-12
申请人： FUJITSU LIMITED
发明人： Asami, Fumitaka , Takagi, Osamu
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/665 , H03K3/356104
摘要： Load terminals of flip-flops P D1 to P D12 of respective stages of an N step counter are cascade-connected via buffers BUF and a load signal LOAD is applied to the load terminals from a load signal generator circuit LDG. The load signal generator circuit LDG has a detector DET for detecting a specific count value which occurs a little before initial value loading of the flip-flop stages of the counter circuit is to be begun. A shift register SHR receives a detection output of the detector DET and the detection output is shifted through the stages of the shift register SHR independence upon clock signals the same as those used for driving the counter circuit. The detection output is delivered from the shift register SHR as a load signal LOAD at the moment at which initial value loading is to be begun. For the duration of the load signal LOAD and a selected period of time subsequent thereto a load control circuit LCT inhibits the application of a detection output from the detector DET to the shift register SHR, thus preventing erroneous loading.
摘要翻译：通过缓冲器BUF级联连接N级计数器的各级的触发器PD1至PD12的负载端子，并且负载信号LOAD从负载信号发生器电路LDG施加到负载端子。负载信号发生器电路LDG具有检测器DET，用于检测在开始计数器电路的触发器级的初始值加载之前稍稍发生的特定计数值。移位寄存器SHR接收到检测器DET的检测输出，并且检测输出在与用于驱动计数器电路的时钟信号相同的时钟信号上独立于移位寄存器SHR的级。在初始值加载开始的时刻，检测输出作为负载信号LOAD从移位寄存器SHR输出。在负载信号LOAD的持续时间和随后的所选择的时间段内，负载控制电路LCT禁止将检测器DET的检测输出施加到移位寄存器SHR，从而防止错误的加载。

8. 发明授权

EP1675266B1 An improved area efficient programmable frequency divider 有权
标题翻译：面积高效可编程分频器
公开(公告)号：EP1675266B1
公开(公告)日：2010-03-10
申请号：EP05107860.8
申请日：2005-08-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Chatterjee, Kallol , Jain, Deependra
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/665 , H03K21/40 , H03K23/667

9. 发明公开

EP1675266A3 An improved area efficient programmable frequency divider 有权
标题翻译：面积高效可编程分频器
公开(公告)号：EP1675266A3
公开(公告)日：2008-09-24
申请号：EP05107860.8
申请日：2005-08-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Chatterjee, Kallol , Jain, Deependra
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/665 , H03K21/40 , H03K23/667
摘要： A programmable high-speed frequency divider, in which stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified to reduce the area and circuit complexity. A start-up circuitry has been introduced within the said frequency-divider to ensure that the frequency-divider will never go into false state.

10. 发明公开

EP0617515A3 Binary counters 失效
标题翻译：二进制计数器
公开(公告)号：EP0617515A3
公开(公告)日：1996-01-24
申请号：EP94300960.5
申请日：1994-02-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Gaglani, Pranay
IPC分类号： H03K23/58 , H03K23/44
CPC分类号： H03K23/44
摘要： A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay structure has a regular configuration suitable for very large scale integration. The fast counter is implemented so as to provide minimal propagation delay at relatively low cost.

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