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1. 发明公开

EP3314665A1 WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS 审中-公开
标题翻译：基于阱的P型晶体管异质结N型晶体管的集成
公开(公告)号：EP3314665A1
公开(公告)日：2018-05-02
申请号：EP15896567.3
申请日：2015-06-26
申请人： INTEL Corporation
发明人： RACHMADY, Willy , METZ, Matthew V. , DEWEY, Gilbert , MOHAPATRA, Chandra S. , KAVALIEROS, Jack T. , MURTHY, Anand S. , RAHHAL-ORABI, Nadia M. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0924 , H01L21/823807 , H01L21/823821 , H01L21/8258 , H01L29/785
摘要： Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

2. 发明公开

EP3300117A1 A HIGH ASPECT RATIO CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF 审中-公开
标题翻译：高纵横比通道半导体器件及其制造方法
公开(公告)号：EP3300117A1
公开(公告)日：2018-03-28
申请号：EP16190164.0
申请日：2016-09-22
申请人： IMEC VZW
发明人： Kunert, M Bernardette , Waldron, Mrs. Niamh , Guo, Mr. Weiming
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L21/84 , H01L29/78
CPC分类号： H01L21/8258 , H01L21/823487 , H01L21/8252 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L29/42392 , H01L29/66522 , H01L29/66666 , H01L29/66742 , H01L29/66795 , H01L29/7827 , H01L29/785 , H01L29/78642
摘要： The invention relates to a semiconductor device and method for manufacturing such a semiconductor device. The method comprises providing a dielectric isolation layer with an opening confined by a first and a second sidewall surface on a semiconductor substrate; providing in the opening on the semiconductor substrate a fin structure protruding above the top surface from the dielectric isolation layer; providing on the dielectric isolation layer a first vertical channel layer along and in contact with the first exposed sidewall surface of the fin structure; the first vertical channel layer comprising a first channel material being different from the fin material; providing a dielectric layer on the dielectric isolation layer adjacent and in contact with the first vertical channel layer, the dielectric layer having a top surface which is lower than the top surface of the first vertical channel layer; removing at least a top portion of the fin structure thereby creating a trench, having a bottom surface being lower than the top surface of the dielectric isolation layer; providing in the trench a dielectric filling material; such that the top surface of the dielectric layer is substantially planarized with the top surface of the dielectric filling material and thereby making the first vertical channel layer freestanding.
摘要翻译：本发明涉及用于制造这种半导体器件的半导体器件和方法。该方法包括提供具有由半导体衬底上的第一和第二侧壁表面限定的开口的电介质隔离层; 在所述半导体衬底上的所述开口中提供从所述电介质隔离层突出到所述顶表面上方的鳍结构; 在所述电介质隔离层上提供沿着所述鳍结构的所述第一暴露侧壁表面且与其接触的第一垂直沟道层; 所述第一垂直沟道层包括不同于所述鳍状材料的第一沟道材料; 在所述介电隔离层上提供与所述第一垂直沟道层相邻并与其接触的介电层，所述介电层具有比所述第一垂直沟道层的所述顶表面低的顶表面; 去除所述鳍状结构的至少顶部部分，由此形成沟槽，所述沟槽具有低于所述电介质隔离层的所述顶表面的底表面; 在沟槽中提供介电填充材料; 使得介电层的顶表面基本上与介电填充材料的顶表面平坦化并且由此使得第一垂直沟道层独立。

3. 发明公开

EP3293758A1 A SEQUENTIAL INTEGRATION PROCESS 审中-公开
标题翻译：顺序整合过程
公开(公告)号：EP3293758A1
公开(公告)日：2018-03-14
申请号：EP17190841.1
申请日：2017-09-13
申请人： IMEC vzw
发明人： WALKE, Amey Mahadev , VANDOOREN, Anne , COLLAERT, Nadine
IPC分类号： H01L21/822 , H01L21/768 , H01L27/06 , H01L21/8258
CPC分类号： H01L27/14875 , B28D1/005 , H01L21/304 , H01L21/76898 , H01L21/8221 , H01L21/8258 , H01L27/0688 , H01L27/0694 , H01L29/41708 , H01L31/02164 , H01L31/022408
摘要： According to the present inventive concept there is provided a sequential integration process comprising:
forming a wafer stack by bonding a first wafer (210) to a second wafer (220) with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region (212) formed on the front side of the first wafer and including a set of semiconductor devices,
subsequent to forming the wafer stack, forming a second device region (232) on a back side of the first wafer, the second device region including a set of semiconductor devices,
forming at least one interconnection layer (234) on the second device region for electrically interconnecting the semiconductor devices of the second device region, and
forming at least one via (240) extending through the wafer stack from the at least one interconnection layer (234) and through the first wafer (210).
摘要翻译：根据本发明构思，提供了一种顺序集成工艺，包括：通过将第一晶片（210）结合到第二晶片（220）来形成晶片堆叠，其中第一晶片的正面面对第二晶片的正面，所述第一晶片包括形成在所述第一晶片的正面上并且包括一组半导体器件的第一器件区域（212），在形成所述晶片堆叠之后，在所述第一晶片的背面形成第二器件区域（232）第一晶片，第二器件区域包括一组半导体器件，在第二器件区域上形成至少一个互连层（234），用于电互连第二器件区域的半导体器件，并形成至少一个通孔（240）从所述至少一个互连层（234）穿过所述晶圆堆叠并穿过所述第一晶圆（210）。

4. 发明公开

EP3095133A4 METHOD OF FORMING AN INTEGRATED CIRCUIT AND RELATED INTEGRATED CIRCUIT 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN SCHALTUNG UNDZUGEHÖRIGEINTEGRIERTE SCHALTUNG
公开(公告)号：EP3095133A4
公开(公告)日：2017-08-30
申请号：EP15737847
申请日：2015-01-14
申请人： MASSACHUSETTS INST TECHNOLOGY , NAT UNIV SINGAPORE , UNIV NANYANG TECH
发明人： ZHANG WENJIA , WANG BING , ZHANG LI , ZHU ZHAOMIN , MICHEL JURGEN , CHUA SOO-JIN , PEH LI-SHIUAN , CHIAH SIAU BEN , LEE ENG KIAN KENNETH
IPC分类号： H01L27/15 , H01L21/822 , H01L21/8258 , H01L27/06 , H01L33/00
CPC分类号： G02B6/12004 , G02B6/12 , G02B6/428 , G02B2006/121 , H01L21/8258 , H01L27/0688 , H01L27/15 , H01L31/03044 , H01L31/035236 , H01L31/0392 , H01L31/12 , H01L31/153 , H01L33/0079 , H01L33/06 , H01L33/12 , H01L33/32
摘要： A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
摘要翻译：公开了形成集成电路的方法（100）。该方法包括：（i）从布置在半导体衬底上的至少第一晶片材料形成至少一对光电子器件，第一晶片材料不同于硅; （ii）蚀刻所述第一晶圆材料以形成待用第二材料填充的第一凹陷; （iii）处理（104）所述第二材料以形成用于耦合所述一对光电器件以限定光学互连的波导; （iv）将具有至少一个晶体管的至少一个经部分处理的CMOS器件层接合（106）到第二半导体衬底以形成集成电路，所述经部分处理的CMOS器件层被布置为与光学互连相邻。还公开了一种集成电路。

5. 发明公开

EP3123507A1 MULTI-DEVICE FLEXIBLE ELECTRONICS SYSTEM ON A CHIP (SOC) PROCESS INTEGRATION 审中-公开
标题翻译： PROZESSINTEGRATIONFÜRFLEXIBLES ELEKTRONIKSYSTEM-ON-CHIP（SOC）MIT MEHREREN BAUELEMENTEN
公开(公告)号：EP3123507A1
公开(公告)日：2017-02-01
申请号：EP14887613.9
申请日：2014-03-27
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , DASGUPTA, Sansaptak , MUKHERJEE, Niloy , DOYLE, Brian S. , RADOSAVLJEVIC, Marko , THEN, Han Wui
IPC分类号： H01L23/48 , H01L23/12 , H01L25/00
CPC分类号： H01L25/0652 , G06F1/1652 , G09F9/301 , G09G3/3648 , H01L21/8221 , H01L21/8258 , H01L23/145 , H01L23/15 , H01L23/49811 , H01L23/4985 , H01L25/00 , H01L25/50 , H01L27/0688 , H01L29/2003 , H01L29/24 , H01L2225/06527 , H01L2225/06555 , H01L2924/0002
摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。可以依次处理多材料堆叠以在单个柔性SOC中形成多个集成电路（IC）装置。通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点置于SOC的公共背面中。堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。可以描述和/或要求保护其他实施例。

6. 发明公开

EP3084806A1 PLANAR HETEROGENEOUS DEVICE 审中-公开
标题翻译： PLANARE异构体VORRICHTUNG
公开(公告)号：EP3084806A1
公开(公告)日：2016-10-26
申请号：EP13899945.3
申请日：2013-12-18
申请人： Intel Corporation
发明人： JUN, Kimin , MORROW, Patrick
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02524 , H01L21/02538 , H01L21/02551 , H01L21/76283 , H01L21/823412 , H01L21/8258 , H01L27/0922 , H01L27/1207 , H01L29/16 , H01L29/20 , H01L29/22 , H01L29/267 , H01L29/78
摘要： In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.
摘要翻译：在一个实施例中，在第一半导体层的顶部上转移第二半导体层（例如，使用层转移技术）。将第二层图案化成所需的孔。在井之间，第一层被暴露。暴露的第一层外延生长到转移的第二层的水平，以完成包括S1和S2的平面异质衬底。可以利用异质材料，使得例如由III-V或IV材料之一形成的P沟道器件与由III-V或IV族材料之一形成的N沟道器件共面。由于第二层被转移到第一层上，该实施例不需要晶格参数依从性。此外，没有（或少量）缓冲和/或异质外延。本文描述了其它实施例。

7. 发明公开

EP2834850A4 MONOLITHIC INTEGRATION OF CMOS AND NON-SILICON DEVICES 审中-公开
标题翻译： CMOS和有机硅器件的单片集成
公开(公告)号：EP2834850A4
公开(公告)日：2015-09-30
申请号：EP13773070
申请日：2013-04-04
申请人： MASSACHUSETTS INST TECHNOLOGY
发明人： FITZGERALD EUGENE A
IPC分类号： H01L21/8238 , H01L21/44 , H01L21/762 , H01L21/8258 , H01L25/00
CPC分类号： H01L25/50 , H01L21/76251 , H01L21/8258 , H01L2924/0002 , H01L2924/00

8. 发明授权

EP1815511B1 A METHOD OF MAKING A SEMICONDUCTOR STRUCTURE FOR HIGH POWER SEMICONDUCTOR DEVICES 有权
标题翻译：一种用于生产半导体结构的高性能半导体器件
公开(公告)号：EP1815511B1
公开(公告)日：2015-09-02
申请号：EP05815152.3
申请日：2005-10-26
申请人： Northrop Grumman Systems Corporation
发明人： CLARKE, Rowland C. , HOWELL, Robert S. , AUMER, Michel E.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/735 , H01L21/82 , H01L21/762 , H01L21/8258 , H01L21/84 , H01L27/06 , H01L29/20
CPC分类号： H01L21/76256 , H01L21/76254 , H01L21/8213 , H01L21/8258 , H01L21/84 , H01L27/0605 , H01L29/2003 , H01L29/6606 , H01L29/66068 , H01L29/735 , H01L29/7787

9. 发明公开

EP2878009A1 MONOLITHIC INTEGRATED CIRCUIT CHIP INTEGRATING MULTIPLE DEVICES 有权
标题翻译：与多个设备单片集成电路芯片
公开(公告)号：EP2878009A1
公开(公告)日：2015-06-03
申请号：EP13731186.6
申请日：2013-05-24
申请人： Raytheon Company
发明人： SAUNDERS, Jeffrey, H.
IPC分类号： H01L21/8258 , H01L27/06 , H01L27/085
CPC分类号： H01L21/8258 , G01S7/032 , H01L27/0605 , H01L27/0623 , H01L27/085 , H01L2924/0002 , H01L2924/00
摘要： A monolithic integrated circuit (IC) chip containing a plurality of transistors, including: a substrate; a first transistor on the substrate; and a second transistor integrally formed on the substrate with the first transistor, the second transistor having a different structure than the first transistor, wherein the first transistor includes a first material system and the second transistor includes a second material system different from the first material system. The monolithic IC chip may further include a third transistor integrally formed on the substrate with the first and second transistors. The first transistor may include gallium nitride (GaN) and the second and third transistors may include silicon carbide (SiC).

10. 发明授权

EP2317554B1 Integrated semiconductor substrate structure and method of manufacturing an integrated semiconductor substrate structure 有权
标题翻译：用于集成半导体衬底结构集成半导体衬底结构及其制造方法
公开(公告)号：EP2317554B1
公开(公告)日：2014-04-09
申请号：EP09174721.2
申请日：2009-10-30
申请人： IMEC
发明人： Degroote, Stefan , Cheng, Kai
IPC分类号： H01L27/06 , H01L21/8252 , H01L21/8258
CPC分类号： H01L27/0605 , H01L21/8252 , H01L21/8258

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