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1. 发明授权

EP0480446B1 Method of fabricating a high-performance insulated-gate-field-effect transistor and transistor fabricated by it 失效
标题翻译：一种用于制造具有绝缘栅晶体管，然后产生一个高性能的场效应晶体管的制造方法
公开(公告)号：EP0480446B1
公开(公告)日：2001-01-31
申请号：EP91117361.5
申请日：1991-10-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： H01L29/08 , H01L29/41 , H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L29/6659 , H01L21/32051 , H01L29/41783 , H01L29/4925 , H01L29/4933 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/78

2. 发明授权

EP0641017B1 Method and apparatus for semiconductor device processing 失效
标题翻译：用于制造半导体装置的方法和设备
公开(公告)号：EP0641017B1
公开(公告)日：2000-05-31
申请号：EP94113310.0
申请日：1994-08-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： H01L21/00
CPC分类号： H01L21/67103

3. 发明授权

EP0641992B1 Warpage and slip dislocation lines measurements in semiconductor processing 失效
标题翻译：在半导体工艺曲率位错线的和测量的
公开(公告)号：EP0641992B1
公开(公告)日：2000-04-12
申请号：EP94114132.7
申请日：1994-09-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： G01B11/16 , G01B11/30 , H01L21/00
CPC分类号： G01B11/306 , G01B11/161

4. 发明授权

EP0583007B1 Temperature sensor calibration device and method 失效
标题翻译：装置和方法用于校准的温度传感器
公开(公告)号：EP0583007B1
公开(公告)日：1997-10-29
申请号：EP93112878.9
申请日：1993-08-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M. , Najm , Habib , Velo, Lino A.
IPC分类号： G01J5/00
CPC分类号： G01K15/005 , G01J5/522 , G01J2005/0048

5. 发明公开

EP0641992A2 Apparatus systems and methods for measuring defects in semiconductor processing 失效
标题翻译：机和Verfahrungssysteme用于测量半导体制造缺陷。
公开(公告)号：EP0641992A2
公开(公告)日：1995-03-08
申请号：EP94114132.7
申请日：1994-09-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： G01B11/16 , G01B11/30
CPC分类号： G01B11/306 , G01B11/161
摘要： A system (22) is provided for measuring defects such as warpage, film stress and slip dislocations in a semiconductor wafer (10), which includes a laser source (24) for generating a primary laser beam. At least one beam splitter (26) splits the primary laser beam into at least first and second beams, the first beam is directed to a first point of wafer surface, and the second beam is directed to a second point of the wafer surface. The at least one beam splitter (26) is further operable to combine a portion of the first beam after reflection from the first point of wafer surface and a portion of the second beam after reflection from the second point of the wafer surface into at least one composite beam for interferometric beam fringe pattern analysis.

6. 发明公开

EP0480446A3 Method of fabricating a high-performance insulated-gate-field-effect transistor and transistor fabricated by it 失效
标题翻译：制造由其制造的高性能绝缘栅场效应晶体管和晶体管的方法
公开(公告)号：EP0480446A3
公开(公告)日：1995-02-15
申请号：EP91117361.5
申请日：1991-10-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： H01L21/336 , H01L21/28 , H01L29/08 , H01L29/60 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/32051 , H01L29/41783 , H01L29/4925 , H01L29/4933 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/78
摘要： An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.
摘要翻译：改进的器件制造方法和晶体管结构36提供浅的重掺杂的源极/漏极结区64和具有高浓度掺杂剂的均匀掺杂的下部栅极区50，其有效地分布在栅极电极/栅极界面51附近。栅极，源极并且晶体管36的漏极端子可以通过使用反应后的难熔金属互连部分98和100而互连到其他相邻或远程设备。本发明的晶体管结构36可以以升高的源极/漏极格式构造以包括抬高的源极 /漏结区87，其可以与主上栅电极区88同时制造。提供的这种提高的源/漏结特征没有增加设备处理复杂度。

7. 发明授权

EP0686999B1 Pattern formation in the fabrication of microelectronic devices 失效
标题翻译：图案生成在微电子组件的制造
公开(公告)号：EP0686999B1
公开(公告)日：2003-08-13
申请号：EP95108351.8
申请日：1995-05-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： H01L21/033 , H01L21/321 , G03F7/00
CPC分类号： H01L21/0337 , G03F7/0042 , G03F7/265 , H01L21/0332 , H01L21/3086 , H01L21/3105 , H01L21/32139 , Y10S430/167 , Y10S430/168 , Y10S438/911 , Y10S438/942 , Y10S438/95 , Y10S438/981

8. 发明公开

EP0746012A3 Improvements relating to silicide formation 失效
标题翻译：硅化改进
公开(公告)号：EP0746012A3
公开(公告)日：1999-01-20
申请号：EP96108737.6
申请日：1996-05-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Paranjpe, Ajit Pramod , Apte, Pushkar Prabhakar , Moslehi, Mehrdad M.
IPC分类号： H01L21/283 , H01L23/532 , H01L21/265 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/66575
摘要： A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide (32) and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide (32) from a higher resistivity phase to a lower resistivity phase. A heavy dopant species (40) is used for the pre-anneal amorphization implant such as arsenic, antimony, or germanium. After the implant, the silicide anneal is performed to accomplish the transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.

9. 发明授权

EP0550058B1 A programmable multizone gas injector for single-wafer semiconductor processing equipment 失效
标题翻译：可编程多区气体喷射器用于植物用于治疗个体的半导体晶片
公开(公告)号：EP0550058B1
公开(公告)日：1998-11-11
申请号：EP92122099.2
申请日：1992-12-29
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M. , Matthews, Robert T. , Davis, Cecil J.
IPC分类号： C23C16/44 , H01L21/00 , C23C16/52
CPC分类号： C23C16/45574 , C23C16/45561 , C23C16/45565 , C23C16/52 , H01L21/67017

10. 发明公开

EP0686999A3 Pattern formation in the fabrication of microelectronic devices 失效
标题翻译： Mustererzeugung in der Herstellung von mikroelektronischen Anordnungen
公开(公告)号：EP0686999A3
公开(公告)日：1997-08-20
申请号：EP95108351.8
申请日：1995-05-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Moslehi, Mehrdad M.
IPC分类号： H01L21/033 , H01L21/321 , G03F7/00
CPC分类号： H01L21/0337 , G03F7/0042 , G03F7/265 , H01L21/0332 , H01L21/3086 , H01L21/3105 , H01L21/32139 , Y10S430/167 , Y10S430/168 , Y10S438/911 , Y10S438/942 , Y10S438/95 , Y10S438/981
摘要： An all-dry microlithography process, where a fluorinated layer 30 is deposited on a processable layer 18 of a semiconductor wafer, and regions of the fluorinated layer 30 are exposed to a masked radiation source so that exposed regions and unexposed areas 31 are formed in the fluorinated layer 30 . An oxide layer is grown on the fluorinated layer, forming thicker region 34 of oxide on the unexposed areas 31 of the fluorinated layer 30 , and forming thinner regions 32 of oxide on the exposed regions of the fluorinated layer 30 . The oxide layer is then etched, removing thinner regions 32 of the oxide layer but leaving at least a fraction of the thicker portions 34 of the oxide layer to be used as a patterned hard mask. Then the exposed fluorinated layer not covered by the patterned oxide hard mask, is etched, to expose areas of the processable layer 18 not covered by the oxide hard mask, for subsequent patterned processing. The subsequent patterned processing may be an etch process for pattern transfer to the processable layer, a doping process to dope the exposed regions of the processable layer, or another process such as a deposition step. The all-dry lithography process can be completed in an integrated environment, such as a cluster tool, resulting in improved manufacturing cycle time and increased yields. The dry photosensitive layer may be deposited using PECVD at low temperatures, and is compatible with all other semiconductor device fabrication process flows.
摘要翻译：将全氟干燥微光刻工艺，其中氟化层30沉积在半导体晶片的可加工层18上，并且氟化层30的区域暴露于掩蔽的辐射源，使得暴露区域和未曝光区域31形成在氟化层30.在氟化层上生长氧化物层，在氟化层30的未曝光区域31上形成氧化物的较厚区域34，并在氟化层30的暴露区域上形成氧化物的较薄区域32.氧化物然后蚀刻层，去除氧化物层的较薄区域32，但留下用作图案化硬掩模的氧化物层的较厚部分34的至少一部分。然后蚀刻未被图案化的氧化物硬掩模覆盖的暴露的氟化层，以露出未被氧化物硬掩模覆盖的可加工层18的区域，以进行后续的图案化处理。随后的图案化处理可以是用于图案转移到可加工层的蚀刻工艺，用于掺杂可加工层的暴露区域的掺杂工艺或诸如沉积步骤的另一工艺。全干式光刻工艺可以在诸如集群工具的集成环境中完成，从而改善制造周期时间并提高产量。可以使用PECVD在低温下沉积干燥的感光层，并且与所有其它半导体器件制造工艺流程兼容。

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