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1. 发明公开

EP2590169A1 Hardware-based methods and apparatus for inter-track interference mitigation in magnetic recording systems 审中-公开
标题翻译：用于磁记录系统磁道之间的干扰减轻的基于硬件的方法和装置
公开(公告)号：EP2590169A1
公开(公告)日：2013-05-08
申请号：EP12186138.9
申请日：2012-09-26
申请人： LSI Corporation
发明人： Worrell, Kurt J. , Haratsch, Erich F. , Xu, Changyou , Singleton, Jefferson E. , Venkatachalam, Kripa , Springberg, David G.
IPC分类号： G11B20/18 , G11B5/09
CPC分类号： G11B5/09 , G11B5/012 , G11B19/045
摘要： Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data to an ITI mitigation circuit using a write data path in the magnetic recording system. The write data path can optionally operate substantially simultaneously with the read data path performing the read operation. The ITI cancellation data comprises, for example, user data and/or media data.
摘要翻译：提供了用于在磁记录系统的轨道间干扰减轻的基于硬件的方法和装置。间轨道干扰（ITI）在磁记录系统通过获得ITI消除数据缓解; 和磁记录系统中使用的写数据路径提供ITI消除数据在ITI消减电路。该写数据通路可任选与执行读操作的读数据路径基本上同时操作。该ITI消除数据包括，例如，用户数据和/或媒体数据。

2. 发明授权

EP2822184B1 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders 有权
标题翻译：对数似然比（LLR）对比LDPC码Decodierung
公开(公告)号：EP2822184B1
公开(公告)日：2017-03-15
申请号：EP14175629.6
申请日：2014-07-03
申请人： LSI Corporation
发明人： Cohen, Earl T. , Haratsch, Erich F. , Alhussien, Abdel-Hakim S.
IPC分类号： H03M13/37 , H03M13/11
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/1111 , H03M13/1142 , H03M13/3723 , H03M13/6306 , H03M13/658 , H03M13/6591

3. 发明公开

EP2822184A1 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders 有权
标题翻译：低密度奇偶校验（LDPC）解码器中的对数似然比（LLR）衰减
公开(公告)号：EP2822184A1
公开(公告)日：2015-01-07
申请号：EP14175629.6
申请日：2014-07-03
申请人： LSI Corporation
发明人： Cohen, Earl T. , Haratsch, Erich F. , Alhussien, Abdel-Hakim S.
IPC分类号： H03M13/37 , H03M13/11
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/1111 , H03M13/1142 , H03M13/3723 , H03M13/6306 , H03M13/658 , H03M13/6591
摘要： Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened LDPC codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. If the LDPC decoding fails, the media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and starts a second LDPC decoding trial using the second set of LLR values. The dampening of LLR values includes scaling by a predetermined scaling factor and decreasing their magnitude by a predetermined amount.
摘要翻译：所描述的实施例提供媒体控制器以读取存储在媒体中的数据。媒体控制器为来自媒体的缩短的码字的每个比特确定一个值。缩短的LDPC码字包括全码字的多个未缩短的比特，其中全码字包括多个未缩短的比特和一个或多个缩短的比特。缩短的比特对应于在缩短的码字中未使用的比特。媒体控制器将缩短码字的每个比特的确定值转换为第一组对数似然比（LLR）值。使用缩短的码字的第一组LLR值对全码字进行解码。如果LDPC解码失败，则媒体控制器衰减对应于码字的非缩短比特的一个或多个LLR值以产生第二组LLR值，并且使用第二组LLR值开始第二LDPC解码试验。 LLR值的衰减包括按预定缩放因子缩放并将其幅度减小预定量。

4. 发明公开

EP2587483A1 Hardware-based inter-track interference mitigation in magnetic recording systems with read channel storage of cancelation data 审中-公开
标题翻译： Hardwarebasierte Interferenzminderung zwischen Spuren in magnetischen Aufzeichnungssystemen mit Lesekanalspeicherung von Kompensationsdaten
公开(公告)号：EP2587483A1
公开(公告)日：2013-05-01
申请号：EP12186043.1
申请日：2012-09-26
申请人： LSI Corporation
发明人： Worrell, Kurt J. , Haratsch, Erich F. , Xu, Changyou , Singleton, Jefferson E. , Venkatachalam, Kripa , Springberg, David G.
IPC分类号： G11B20/18 , G11B5/09
CPC分类号： G11B5/09 , G11B5/012 , G11B19/045
摘要： Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) cancellation data is stored in a memory of a read channel of a magnetic recording system. The memory can be in a write data path or a read data path of the read channel. The inter-track interference cancellation data is optionally provided to an inter-track interference mitigation circuit using at least a portion of a write data path, for example, based on a control signal. The storage of the inter-track interference cancellation data can be in response to a second control signal.
摘要翻译：提供基于硬件的方法和装置用于磁记录系统中的轨道间干扰减轻。轨道间干扰（ITI）抵消数据被存储在磁记录系统的读通道的存储器中。存储器可以在读取通道的写入数据路径或读取数据路径中。可以例如基于控制信号，使用写入数据路径的至少一部分，将轨道间干扰消除数据可选地提供给轨道间干扰减轻电路。轨道间干扰消除数据的存储可以响应于第二控制信号。

5. 发明公开

EP2562756A2 Read channel with oversampled analog to digital conversion 审中-公开
标题翻译：模拟数字万花筒
公开(公告)号：EP2562756A2
公开(公告)日：2013-02-27
申请号：EP12180633.5
申请日：2012-08-16
申请人： LSI Corporation
发明人： Bailey James A. , Aravind Nayak Ratnakar , Haratsch, Erich F.
IPC分类号： G11B20/10
CPC分类号： G11B20/10009
摘要： Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.
摘要翻译：提供了用于使用过采样模数转换处理读通道中的信号的方法和装置。对模拟输入信号进行过采样的模数转换，以在给定位间隔上产生对应于模拟输入信号的多个数字样本。然后可以将数据检测算法应用于一个或多个数字样本以获得检测到的输出。过采样的模数转换通过将均衡和/或滤波处理的至少一部分转移到数字域来简化了模拟设计。

6. 发明公开

EP2562756A3 Read channel with oversampled analog to digital conversion 审中-公开
标题翻译：读通道过采样模拟到数字转换
公开(公告)号：EP2562756A3
公开(公告)日：2015-12-09
申请号：EP12180633.5
申请日：2012-08-16
申请人： LSI Corporation
发明人： Bailey James A. , Aravind Nayak Ratnakar , Haratsch, Erich F.
IPC分类号： G11B20/10
CPC分类号： G11B20/10009
摘要： Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.

7. 发明授权

EP2763042B1 Detection and decoding in flash memories with selective binary and non-binary decoding 有权
标题翻译：检测和解码在具有选择性二进制和非二进制编码闪速存储器
公开(公告)号：EP2763042B1
公开(公告)日：2015-09-09
申请号：EP14153544.3
申请日：2014-01-31
申请人： LSI Corporation
发明人： Alhussien, Abdel Hakim S. , Li, Zongwang , Haratsch, Erich F. , Danjean, Ludovic
IPC分类号： G06F11/10
CPC分类号： G06F11/1028 , H03M13/1171 , H03M13/3723 , H03M13/611 , H03M13/612 , H03M13/63

8. 发明公开

EP2899890A1 Systems and methods for latency based data recycling in a solid state memory system 审中-公开
标题翻译： Systeme und Verfahrenfürdas回收latenzbasierter Daten in einemFestkörperspeichersystem
公开(公告)号：EP2899890A1
公开(公告)日：2015-07-29
申请号：EP14189389.1
申请日：2014-10-17
申请人： LSI Corporation
发明人： Cai, Yu , Wu, Yunxiang , Chen, Ning , Haratsch, Erich F. , Chen, Zhengang
IPC分类号： H03M13/00 , H03M13/11 , H03M7/30
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/7205 , G11C16/08 , G11C29/52 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1128 , H03M13/3746 , H03M13/6505
摘要： Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory.
摘要翻译：一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。

9. 发明公开

EP2822184A9 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders 有权
标题翻译：用于解码LDPC对数似然率（LLR）的衰减
公开(公告)号：EP2822184A9
公开(公告)日：2015-06-10
申请号：EP14175629.6
申请日：2014-07-03
申请人： LSI Corporation
发明人： Cohen, Earl T. , Haratsch, Erich F. , Alhussien, Abdel-Hakim S.
IPC分类号： H03M13/37 , H03M13/11
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/1111 , H03M13/1142 , H03M13/3723 , H03M13/6306 , H03M13/658 , H03M13/6591
摘要： Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened LDPC codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. If the LDPC decoding fails, the media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and starts a second LDPC decoding trial using the second set of LLR values. The dampening of LLR values includes scaling by a predetermined scaling factor and decreasing their magnitude by a predetermined amount.

10. 发明公开

EP2763042A9 Detection and decoding in flash memories with selective binary and non-binary decoding 有权
标题翻译：检测和解码在具有选择性二进制和非二进制编码闪速存储器
公开(公告)号：EP2763042A9
公开(公告)日：2014-12-03
申请号：EP14153544.3
申请日：2014-01-31
申请人： LSI Corporation
发明人： Alhussien, Abdel Hakim S. , Li, Zongwang , Haratsch, Erich F. , Danjean, Ludovic
IPC分类号： G06F11/10
CPC分类号： G06F11/1028 , H03M13/1171 , H03M13/3723 , H03M13/611 , H03M13/612 , H03M13/63
摘要： Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.

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