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1. 发明公开

CN112350967A 一种HDB3编码、解码方法及装置无效
公开(公告)号：CN112350967A
公开(公告)日：2021-02-09
申请号：CN201910720262.8
申请日：2019-08-06
申请人：天津光电通信技术有限公司
发明人：李羚梅 , 尚进 , 刘博 , 刘彧涵 , 范玉进 , 赵保磊 , 刘政鹏 , 蒋航 , 刘彩红
IPC分类号： H04L25/49 , H04L25/493 , H03M5/18
摘要：本发明提供一种HDB3编码、解码方法及装置，其中，所述HDB3编码方法包括：将电子信号转换为AMI码；检测所述AMI码中数字信号0的连续情况，在0的连续个数不大于3时，保持数字信号0不变；在0的连续个数大于3时，按照顺序将每4个数字信号0作为一个小节，将最后一个数字信号0用破坏脉冲代替，所述破坏脉冲的极性与前一个相邻的非0码极性相同；在所述破坏脉冲的极性不满足相邻破坏脉冲交替时，将所述小节中的首个数字信号0用调节脉冲代替，所述调节脉冲的极性与同一小节的破坏脉冲的极性相同。有利于接收端的定时信号提取，对定时信号的恢复十分有利。更加适用于数字通信。

2. 实用新型

CN205212819U 一种基于CPLD的HDB3编译码器电路失效
公开(公告)号：CN205212819U
公开(公告)日：2016-05-04
申请号：CN201521049977.9
申请日：2015-12-10
申请人：重庆电子工程职业学院
发明人：刘梅华
IPC分类号： H03M5/18
摘要：本实用新型公开一种基于CPLD的HDB3编译码器电路，包括CPLD处理器和单片机；单片机通过SPI串行通信接口与CPLD处理器实现电连接；CPLD处理器包括HDB3编码器模块和HDB3译码器模块。本实用新型具有电路结构简单，系统稳定性高，并且便于用户根据具体设计需要进行修改调试的优点。此外本实用新型还具有能实现对HDB3的编译码电路数据误码率及传输速率自动分析的优点。

3. 发明申请

WO2007125366A2 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO2007125366A2
公开(公告)日：2007-11-08
申请号：PCT/GB2007050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL BRIAN STEPHEN
发明人： CARROLL BRIAN STEPHEN
IPC分类号： H03M5/18 , H03M1/68 , H03M7/06 , H04L25/49
CPC分类号： H04L25/4925 , H03M1/745 , H04L27/2626
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.
摘要翻译：数模转换器本发明一般涉及数模转换器（DAC）。更具体地说，它涉及具有减小的小信号差分非线性的差分，电流导向DAC。一种差分电流转向数模转换器（DAC），该DAC包括：数字输入端，用于接收包含多个位的二进制码，该位定义用于转换为有符号差分模拟输出信号的带符号数字值; 一对差分模拟输出线，用于提供所述差分模拟输出; 以及一组二进制加权的可操作的恒定恒定电流发生器，每一个都耦合到所述差分输出线并具有一个控制输入端，用于接收从所述数字输入端导出的信号，以响应于所述二进制输入码来控制对所述差分输出线路的电流转向; 其特征在于，一个所述可操纵的基本恒定的电流发生器包括三元基本上恒定的电流发生器，其被配置为响应于所述控制输入上的三进制信号产生三态差动电流; 其中每个所述三进制电流发生器与所述二进制码的位相关联; 并且其中所述DAC还包括耦合在所述DAC数字输入和所述可控电流发生器的所述控制输入之间的代码转换器，以将所述二进制输入代码转换为三进制代码以控制所述可转向电流发生器。

4. 发明申请

WO2007125366A3 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
公开(公告)号：WO2007125366A3
公开(公告)日：2007-11-08
申请号：PCT/GB2007/050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL, Brian Stephen
发明人： CARROLL, Brian Stephen
IPC分类号： H03M5/18 , H03M7/06 , H04L25/49 , H03M1/68
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.

5. 发明申请

WO2018161153A1 MODULATION FOR A DATA BIT STREAM 审中-公开
公开(公告)号：WO2018161153A1
公开(公告)日：2018-09-13
申请号：PCT/CA2018/050218
申请日：2018-02-26
申请人： BLACKBERRY LIMITED
发明人： QU, Shouxing
IPC分类号： H03M5/18 , H04L27/02
摘要： In some examples, a binary bit stream of input bits is encoded into a three-amplitude bipolar symbol stream of symbols, the encoding using a coding rule that specifies setting a value of a respective symbol of the symbol stream based on a respective input bit of the binary bit stream and a prior input bit of the binary bit stream that is prior to the respective input bit, the coding rule further specifying that adjacent non-zero pulses keep the same polarity. A radio frequency (RF) carrier signal is modulated using the symbol stream to produce a modulated RF signal.

6. 发明申请

WO98044635A1 DUOBINARY CODING AND MODULATION TECHNIQUE FOR OPTICAL COMMUNICATION SYSTEMS 审中-公开
标题翻译：光通信系统的移动编码和调制技术
公开(公告)号：WO98044635A1
公开(公告)日：1998-10-08
申请号：PCT/CA1998/000275
申请日：1998-03-25
IPC分类号： G02F1/01 , H03M5/16 , H03M5/18 , H04B10/00 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H04B10/155 , H04L25/497 , G02F1/225
CPC分类号： H04B10/5055 , H03M5/18 , H04B10/505 , H04B10/5167
摘要： A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit yk =0 when the corresponding bit xk =0; bits yk alternatively assume a logical level "+1" and "-1" whenever an input bit xk-1=0 changes to xk=1, and the output bit yk maintains the logical level "+1" or "-1" whenever the corresponding bit xk maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving an M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.
摘要翻译：提供了一种用于对二进制输入序列x（0,1）进行编码以获得双二进制输出序列y（+ 1,0，-1）的方法。当对应的位xk = 0时，双向编码技术总是提供输出位yk = 0; 只要输入位xk-1 = 0改变为xk = 1，位yk或者假设逻辑电平“+1”和“-1”，并且输出位yk每当维持逻辑电平“+1”或“-1” 对应的位xk保持逻辑电平“1”。还提供了用于将二进制输入序列x（0,1）编码到双二进制输出序列y（+ 1,0，-1）的编码装置，包括用于产生二进制开关信号的D型触发器。第一AND电路接收输入序列和开关信号，并提供第一二进制序列a（0,1），而第二AND电路接收输入序列和开关信号的补码，并提供第二二进制序列b（ 0,1）。将这些第一和第二二进制序列应用于加法器以获得输出序列y（+ 1,0，-1）。还提供了一种用于使用虚拟接地电平差分驱动M-Z调制器的方法，其将峰 - 峰驱动电压降低了二倍。

7. 发明授权

US5160929A System for parallel communication of binary data via trinary transmission lines 失效
标题翻译：用于通过三线传输线并行通信二进制数据的系统
公开(公告)号：US5160929A
公开(公告)日：1992-11-03
申请号：US680431
申请日：1991-04-04
申请人： John F. Costello
发明人： John F. Costello
IPC分类号： H03M5/18 , H04L5/02 , H04L25/49
CPC分类号： H03M5/18 , H04L25/4923 , H04L5/02
摘要： Binary encoded information having a word size of 3N bits, where "N" is a positive integer, plus a parallel data clock are converted to corresponding control signals. Signal drivers with three-state outputs respond to the control signals and communicate corresponding signals via transmission lines, one transmission line per signal driver, to receiving circuits capable of detecting three-state signals, an embodiment of said circuits produce bipolar signals corresponding to the state of the transmission lines with which they communicate. A code converter produces binary signals and a data clock corresponding to the bipolar signals from the receiving circuits. The net result is that the binary word and data clock produced at a receiving end of the transmission lines logically matches the binary code and data clock applied at a sendng end, and that the produced data clock has the same timing relationship with the received binary word as does the originating data clock have with the originating binary word.
摘要翻译：具有3N比特的字大小的二进制编码信息，其中“N”是正整数，加上并行数据时钟被转换成相应的控制信号。具有三态输出的信号驱动器响应控制信号并且通过传输线（每个信号驱动器的一个传输线）到能够检测三态信号的接收电路传送相应的信号，所述电路的实施例产生对应于该状态的双极信号与它们通信的传输线路。代码转换器产生对应于来自接收电路的双极性信号的二进制信号和数据时钟。最终的结果是，在传输线的接收端产生的二进制字和数据时钟逻辑地匹配在发送端应用的二进制码和数据时钟，并且所产生的数据时钟与所接收的二进制字具有相同的定时关系始发数据时钟与始发二进制字一样。

8. 发明授权

US5119380A Zero string error detection circuit 失效
标题翻译：零点错误检测电路
公开(公告)号：US5119380A
公开(公告)日：1992-06-02
申请号：US408080
申请日：1989-09-14
申请人： Satoshi Ohwada , Takenao Takemura , Toru Kosugi
发明人： Satoshi Ohwada , Takenao Takemura , Toru Kosugi
IPC分类号： H03M5/16 , H03M5/18 , H04L1/00 , H04L7/00 , H04L25/49
CPC分类号： H04L7/0083 , H04L25/4925
摘要： A zero string error detection circuit which detects a specified number of zeros occurring in succession in bipolar data. The detection circuit has a relatively small gate size achieved by making the shift registers in the B8ZS or B6ZS code conversion circuit serve also for zero string monitoring. The zero string error detection circuit includes a pair of shift registers which receive serial bipolar data and convert it to parallel data composed of a specified number of bits, a code detector which, upon detecting a specific code from the parallel outputs of the shift registers, issues a reset signal to the shift registers to make the outputs of the shift registers zero, a zero string monitor which issue a zero string error detection signal when the outputs of the shift registers become zero, and a gate which inhibits the zero string monitor from issuing the zero string error detection signal during a specific period when the code detector issues a reset signal.

9. 发明授权

US4972106A Binary-to-ternary converter for combining two binary signals 失效
标题翻译：用于组合两个二进制信号的二进制到三进制转换器
公开(公告)号：US4972106A
公开(公告)日：1990-11-20
申请号：US326184
申请日：1989-03-17
申请人： Jan B. F. W. Ruijs
发明人： Jan B. F. W. Ruijs
IPC分类号： H03M7/06 , H03M5/16 , H03M5/18 , H03M7/14 , H04L5/22
CPC分类号： H03M5/18 , H04L5/22
摘要： A binary-to-ternary converter arrangement which achieves protective resistance against high outside voltages without having to compromise the voltage level of the positive and negative output ternary pulses. In so achieving, the minimum amplitude requirement of a CCITT recommendation of an output pulse for a given supply voltage is satisfied. This converter arrangement includes a parallel circuit of first and second series circuits. The first series circuit forms a main current path of two transistors and the second series circuit forms a current path of a diode, two resistors, and a third transistor. The different elements of these two circuits, along with a capacitor element, are interconnected in such a way as to eliminate the need for the use of a transformer altogether. The control electrodes of the first and second transistors serve as input ports and the junction port of the two resistors serves as the output port.

10. 发明授权

US4808854A Trinary inverter 失效
标题翻译：三相逆变器
公开(公告)号：US4808854A
公开(公告)日：1989-02-28
申请号：US21976
申请日：1987-03-05
申请人： Frederick G. Reinagel
发明人： Frederick G. Reinagel
IPC分类号： H03M5/18 , H03K17/66 , H03K17/13 , H03K17/687 , H03K19/094
CPC分类号： H03M5/18
摘要： A trinary inverter for a digital logic circuit of the type having relatively positive, negative and zero signal voltage values is implemented with CMOS transistors and has the advantages of low power dissipation and low output impedance in the zero signal state. The inverter comprises first, second and third inverter branches, where each branch is formed of a pair of complementary MOS field effect transistors. The inverted output signals from each branch are used to produce a device output signal having the desired voltage transfer characteristics.
摘要翻译：具有相对正，负和零信号电压值的数字逻辑电路的三次逆变器由CMOS晶体管实现，并且在零信号状态下具有低功耗和低输出阻抗的优点。逆变器包括第一，第二和第三反相器分支，其中每个分支由一对互补MOS场效应晶体管形成。来自每个分支的反相输出信号用于产生具有所需电压传递特性的器件输出信号。

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