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1. 发明公开

EP2507737A2 HOOKING NONEXPORTED FUNCTIONS BY THE OFFSET OF THE FUNCTION 审中-公开
标题翻译：基于函数的偏移隐藏非提交函数
公开(公告)号：EP2507737A2
公开(公告)日：2012-10-10
申请号：EP10835122.2
申请日：2010-12-02
申请人： McAfee, Inc.
发明人： NOJIRI, Daisuke
IPC分类号： G06F21/20 , G06F7/493 , G06F13/14
CPC分类号： G06F21/54 , G06F21/566
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obfuscated malware. In one aspect, a method includes accessing offset data associated with a binary executable, the offset data including an offset of a nonexported function; and modifying instructions at the offset. In another aspect, a method includes analyzing a reference generated for a binary executable, identifying a unique identifier for the binary executable, determining an offset of a nonexported function in the binary executable, and generating offset data that includes the offset and the unique identifier.
摘要翻译：方法，系统和装置，包括编码在计算机存储介质上的计算机程序，用于混淆恶意软件。在一个方面，一种方法包括访问与二进制可执行文件相关联的偏移数据，所述偏移数据包括非出口函数的偏移量; 并修改偏移量处的指令。在另一方面，一种方法包括分析为二进制可执行文件生成的参考，识别二进制可执行文件的唯一标识符，确定二进制可执行文件中非出口函数的偏移量，以及生成包括偏移量和唯一标识符的偏移量数据。

2. 发明公开

EP2507737A4 HOOKING NONEXPORTED FUNCTIONS BY THE OFFSET OF THE FUNCTION 审中-公开
标题翻译：澳大利亚新西兰福克斯顿
公开(公告)号：EP2507737A4
公开(公告)日：2014-04-02
申请号：EP10835122
申请日：2010-12-02
申请人： MCAFEE INC
发明人： NOJIRI DAISUKE
IPC分类号： G06F7/493 , G06F13/14 , G06F21/54 , G06F21/56
CPC分类号： G06F21/54 , G06F21/566
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obfuscated malware. In one aspect, a method includes accessing offset data associated with a binary executable, the offset data including an offset of a nonexported function; and modifying instructions at the offset. In another aspect, a method includes analyzing a reference generated for a binary executable, identifying a unique identifier for the binary executable, determining an offset of a nonexported function in the binary executable, and generating offset data that includes the offset and the unique identifier.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于混淆的恶意软件。一方面，一种方法包括访问与二进制可执行文件相关联的偏移数据，所述偏移数据包括非输出函数的偏移量; 并修改偏移处的指令。在另一方面，一种方法包括分析为二进制可执行文件生成的参考，识别二进制可执行文件的唯一标识符，确定二进制可执行文件中的非输出功能的偏移量，以及生成包括偏移量和唯一标识符的偏移数据。

3. 发明申请

WO2011068967A3 HOOKING NONEXPORTED FUNCTIONS BY THE OFFSET OF THE FUNCTION 审中-公开
公开(公告)号：WO2011068967A3
公开(公告)日：2011-06-09
申请号：PCT/US2010/058731
申请日：2010-12-02
申请人： MCAFEE, INC. , NOJIRI, Daisuke
发明人： NOJIRI, Daisuke
IPC分类号： G06F21/20 , G06F7/493 , G06F13/14
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obfuscated malware. In one aspect, a method includes accessing offset data associated with a binary executable, the offset data including an offset of a nonexported function; and modifying instructions at the offset. In another aspect, a method includes analyzing a reference generated for a binary executable, identifying a unique identifier for the binary executable, determining an offset of a nonexported function in the binary executable, and generating offset data that includes the offset and the unique identifier.

4. 发明申请

WO2011068967A2 HOOKING NONEXPORTED FUNCTIONS BY THE OFFSET OF THE FUNCTION 审中-公开
标题翻译：通过功能的偏移来查看非特征函数
公开(公告)号：WO2011068967A2
公开(公告)日：2011-06-09
申请号：PCT/US2010058731
申请日：2010-12-02
申请人： MCAFEE INC , NOJIRI DAISUKE
发明人： NOJIRI DAISUKE
IPC分类号： G06F21/20 , G06F7/493 , G06F13/14
CPC分类号： G06F21/54 , G06F21/566
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obfuscated malware. In one aspect, a method includes accessing offset data associated with a binary executable, the offset data including an offset of a nonexported function; and modifying instructions at the offset. In another aspect, a method includes analyzing a reference generated for a binary executable, identifying a unique identifier for the binary executable, determining an offset of a nonexported function in the binary executable, and generating offset data that includes the offset and the unique identifier.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于混淆的恶意软件。一方面，一种方法包括访问与二进制可执行文件相关联的偏移数据，所述偏移数据包括非输出函数的偏移量; 并修改偏移处的指令。在另一方面，一种方法包括分析为二进制可执行文件生成的参考，识别二进制可执行文件的唯一标识符，确定二进制可执行文件中的非输出功能的偏移量，以及生成包括偏移量和唯一标识符的偏移数据。

5. 发明授权

US5515520A Data processing system for single-precision and double-precision data 失效
标题翻译：数据处理系统，用于单精度和双精度数据
公开(公告)号：US5515520A
公开(公告)日：1996-05-07
申请号：US337411
申请日：1994-11-07
申请人： Koichi Hatta , Koichi Kuroiwa
发明人： Koichi Hatta , Koichi Kuroiwa
IPC分类号： G06F7/00 , G06F7/483 , G06F7/493 , G06F7/509 , G06F7/57 , G06F7/76 , G06F9/38 , G06F3/00
CPC分类号： G06F7/483 , G06F9/3877 , G06F2207/382
摘要： A data processing system includes a single-precision operation unit, a double-precision operation unit, a single-precision data to double-precision data conversion unit, and a double-precision data to single-precision data conversion unit. When two single-precision operations are simultaneously carried out, the single-precision operation unit performs a single-precision operation upon a group of single-precision data, and the double-precision operation unit with the single-precision data to double-precision data conversion unit and the double-precision data to single-precision data conversion unit perform a single-precision operation upon the other group of single-precision data. When a double-precision operation is carried out, the double-precision operation unit performs a double-precision operation upon a group of double-precision data.
摘要翻译：数据处理系统包括单精度运算单元，双精度运算单元，单精度数据双精度数据转换单元，双精度数据单精度数据转换单元。当同时执行两个单精度操作时，单精度运算单元对一组单精度数据执行单精度运算，双精度运算单元将单精度数据转换为双精度数据转换单元和双精度数据到单精度数据转换单元对另一组单精度数据执行单精度运算。当进行双精度运算时，双精度运算部对一组双精度数据进行双精度运算。

6. 发明授权

US5034912A Signal processing circuit for multiplication 失效
标题翻译：用于乘法的信号处理电路
公开(公告)号：US5034912A
公开(公告)日：1991-07-23
申请号：US462379
申请日：1990-01-09
申请人： Sumitaka Takeuchi , Hiroyuki Kouno
发明人： Sumitaka Takeuchi , Hiroyuki Kouno
IPC分类号： G06F7/53 , G06F7/493 , G06F7/52 , G06F7/523 , G06F17/10 , G06J1/00 , H03H17/02
CPC分类号： G06F7/53 , G06J1/00
摘要： A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation. The circuit for generating the signal indicative of the result of multiplication includes a circuit for logically processing, by logic gates, the control signal and the digital multiplicand. The logic gate circuit includes a circuit for detecting coincidence/non-coincidence between a pattern of the generated control signal and a bit pattern of the digital multiplicand, and a circuit responsive to the output of the detecting circuit for activating one of a plurality of possible signals indicating the results of multiplication.
摘要翻译：不需要数模转换器的乘法处理电路包括用于将数字乘法系数乘以数字乘法器并输出乘法结果作为模拟电流信号的电路。乘法处理电路包括用于解码数字乘法系数以产生一个或多个控制信号的电路，响应于数字被乘数的电路和产生的控制信号，用于产生以十进制格式表示乘法结果的信号数字乘法器的数字乘法系数，以及用于将表示乘法结果的信号转换成相应幅度的模拟电流信号的电路。每个控制信号以十进制形式表示至少一个数字乘法系数。用于产生指示乘法结果的信号的电路包括逻辑门逻辑处理控制信号和数字被乘数的电路。逻辑门电路包括用于检测所产生的控制信号的模式与数字被乘数的位模式之间的符合/非重合的电路，以及响应于检测电路的输出的电路，用于激活多个可能的指示乘法结果的信号。

7. 发明授权

US4866651A Method and circuit arrangement for adding floating point numbers 失效
标题翻译：添加浮点数的方法和电路布置
公开(公告)号：US4866651A
公开(公告)日：1989-09-12
申请号：US89649
申请日：1987-08-26
申请人： J. Hartmut Bleher , Axel T. Gerlicher , Siegfried M. Rump , Dieter K. Unkauf
发明人： J. Hartmut Bleher , Axel T. Gerlicher , Siegfried M. Rump , Dieter K. Unkauf
IPC分类号： G06F7/485 , G06F7/493 , G06F7/50 , G06F7/508 , G06F7/38
CPC分类号： G06F7/485
摘要： For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.
摘要翻译：为了连续地添加一系列浮点数，使用浮点加法器级（图2），除了两个浮点操作数的和之外，它还将从较小的操作数中截取的余数作为浮点数。为了获得操作数的精确总和，这些余数以中间和的形式相加。用于并联操作的电路装置包括串联连接的浮点加法器级（图6），中间和出现在每级的输出端，中间余数被缓冲。在每种情况下，剩余物都传递到下一个阶段，它们的值减少直到它们为零。串行操作装置（图8）包括用于缓冲中间和和最终结果的单个加法器级（30）和寄存器堆栈（34）。发生的余数存储在加法器级的输出端的余数寄存器（32）中，并加到中间和直到余数为零。随后，将新的操作数应用于加法器级的输入。

8. 发明授权

US4546447A Division apparatus 失效
标题翻译：司仪器
公开(公告)号：US4546447A
公开(公告)日：1985-10-08
申请号：US459149
申请日：1983-01-19
申请人： Hideo Sawada
发明人： Hideo Sawada
IPC分类号： G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F7/4917
摘要： A division apparatus. A quotient of one digit and a remainder are determined by repeating execution of a single type processing of adding an integral multiple of a divisor and an intermediate remainder. The apparatus includes first, second and third registers for storing a dividend or the intermediate remainder, the integral multiple of a divisor and a carry resulted from a preceding operation, respectively, a selection circuit for selecting the complement of the integral multiple of the divisor when the carry is zero while selecting the integral multiple of the divisor when the carry is 0, an arithmetic circuit for performing adding operation on the output of the selection circuit and the content of the first register with the carry being served as the initial carry, and a counter for counting a number which corresponds to the integral multiple of the divisor. The result of the arithmetic operation which is executed in dependence on the value assumed by the carry is placed in the first register. The quotient is determined on the basis of the content of the counter.
摘要翻译：分割装置。通过重复执行添加除数和中间余数的整数倍的单一类型处理来确定一位数和余数的商。该装置包括用于分别存储除数或中间余数的第一，第二和第三寄存器，分别由先前操作产生的除数的整数倍和进位，用于选择除数积分倍数的补数的选择电路，当进位为0时选择除数的整数倍时，进位为零，用于对选择电路的输出执行加法运算的运算电路和作为初始进位的进位的第一寄存器的内容，以及用于对与除数的整数倍相对应的数字进行计数的计数器。根据进位所假设的值执行的算术运算结果位于第一个寄存器中。商根据计数器的内容确定。

9. 发明授权

US4456955A Alignment of one operand of a two operand arithmetic unit 失效
标题翻译：两个操作数运算单元的一个操作数对齐
公开(公告)号：US4456955A
公开(公告)日：1984-06-26
申请号：US294053
申请日：1981-08-18
申请人： Tomoatsu Yanagita , Motonobu Nagafuji
发明人： Tomoatsu Yanagita , Motonobu Nagafuji
IPC分类号： G06F7/38 , G06F7/00 , G06F7/48 , G06F7/493 , G06F7/50 , G06F7/506 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/34 , G06F13/00
CPC分类号： G06F9/3001 , G06F7/48 , G06F7/49936
摘要： A data processing system has an arithmetic operating unit to process a plurality of bytes at a time and carries out an arithmetic operation on first and second operands each starting from any desired address on a main memory and having any desired number of byte length. The second operand is aligned to an operand position of the first operand and the aligned second operand is supplied to the operating unit while the first operand is supplied as it is to the operating unit. Since the second operand is aligned to the operand position of the first operand before it is processed in the operating unit, the number of times of alignment is reduced.
摘要翻译：数据处理系统具有算术运算单元，用于一次处理多个字节，并对从主存储器上的任何所需地址开始并且具有任何期望数量的字节长度的第一和第二操作数执行算术运算。第二操作数与第一操作数的操作数位置对齐，并且将对准的第二操作数提供给操作单元，同时将第一操作数原样提供给操作单元。由于第二操作数在操作单元处理之前与第一操作数的操作数位置对齐，因此减少对准次数。

10. 发明授权

US4409668A Round-off apparatus for data processors 失效
标题翻译：数据处理器的四舍五入装置
公开(公告)号：US4409668A
公开(公告)日：1983-10-11
申请号：US242142
申请日：1981-03-09
申请人： Junichi Yoshida
发明人： Junichi Yoshida
IPC分类号： G06F7/38 , G06F3/14 , G06F7/483 , G06F7/493 , G06F7/508 , G06F15/02 , G06F7/48
CPC分类号： G06F3/1407
摘要： A round-off type of numeric data display apparatus which has at least X, Y, Z and K registers, and which stores in said X register a previous data item obtained by a previous one of arithmetic operations convergently producing a result in turn, stores in said Y register an immediately succeeding data item obtained by an immediately succeeding one to said previous one of said arithmetic operations, stores in said K register that number of digit-place data items to be rounded-off of said immediately succeeding data item which has been obtained by the arithmetic operation in an arithmetic-operational section connected to said X, Y, Z and K registers, subjects said immediately succeeding data item to rounding-off operation in said arithmetic-operational section on the basis of the contents item of said K register and stores the result of said rounding-off operation in said Z register, transfers the contents item of said Z register and a decimal point code of said Y register to a display buffer connected to said Y and Z registers, and displays only numeric data of reliable digit-place number from a display section connected to said display buffer.
摘要翻译：具有至少X，Y，Z和K寄存器的四舍五入的数字数据显示装置，并且在所述X寄存器中存储由前一个算术运算获得的先前数据项，依次收敛产生结果，存储在所述Y寄存器中，通过紧随其后的一个到所述前一个所述算术运算获得的紧随其后的数据项在所述K个寄存器中存储所述紧随其后的数据项的四舍五入的数位数据项的数目，通过在与所述X，Y，Z和K寄存器连接的算术运算部分中的算术运算来获得，所述算术运算部分将所述紧接着的数据项目的对象基于所述算术运算部分的内容项目进行舍入运算， K寄存器并将所述舍入运算的结果存储在所述Z寄存器中，将所述Z寄存器的内容项和所述Y寄存器的小数点代码传送到显示器bu 连接到所述Y和Z寄存器，并且仅从连接到所述显示缓冲器的显示部分仅显示可靠的数字位数的数字数据。

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