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1. 发明申请

WO1995020270A1 PIPELINED ANALOG-TO-DIGITAL CONVERTER WITH CURVEFIT DIGITAL CORRECTION 审中-公开
标题翻译：具有曲线数字校正的管线模数转换器
公开(公告)号：WO1995020270A1
公开(公告)日：1995-07-27
申请号：PCT/US1994010318
申请日：1994-09-12
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , MAYES, Michael, K. , CHIN, Sing, W.
IPC分类号： H03M01/10
CPC分类号： H03M1/1028 , H03M1/44
摘要： An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying +/-Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured. In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, par example, capacitor value voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit stages, and using these voltage coefficients to further adjust the digital output word, providing an even more accurate digital representation of the analog input signal being mesured.
摘要翻译：一种ADC系统，其中接收和数字操作原始ADC数据，以提高所得数字输出字的精度。在一个实施例中，本发明的数字操作是对已经预先调整了由于使用小于理想的阶段间增益引起的错误的数据执行的。在一个实施例中，仅基于多个最高有效位阶段而不是所有阶段的误差执行数字校正，因为数字输出字对误差的影响对于不太重要的阶段而言是重要的。根据本发明的一个实施例，通过将+/- Vref作为输入信号施加到ADC来确定偏移误差和满刻度误差。这些值允许来自ADC的原始数字数据在硬件或软件中进行补偿，以提供正在测量的模拟输入电压的更准确的数字表示。根据本发明的另一个实施例，通过在校正较低有效位级之后确定ADC的MSB级的电容器值电压系数的大小，并且使用这些电压系数进一步调整来消除二阶误差数字输出字，提供被模拟的模拟输入信号的更准确的数字表示。

2. 发明申请

WO1994027373A1 ALGORITHMIC A/D CONVERTER WITH DIGITALLY CALIBRATED OUTPUT 审中-公开
标题翻译：具有数字校准输出的算法A / D转换器
公开(公告)号：WO1994027373A1
公开(公告)日：1994-11-24
申请号：PCT/US1994005373
申请日：1994-05-12
申请人： ANALOG DEVICES, INCORPORATED
发明人： ANALOG DEVICES, INCORPORATED , LEE, Hae-Seung
IPC分类号： H03M01/10
CPC分类号： H03M1/1038 , H03M1/442
摘要： A multistage pipelined algorithmic A/D converter (34, 36) is digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. The degree of capacitor mismatch is determined through a sequence of measurements for each stage to be calibrated. After the measurements are made the values are stored in a memory device for use during subsequent conversions to cancel the errors due to offset and capacitor mismatch.
摘要翻译：多级流水线算法A / D转换器（34,36）进行数字校准，以避免由于电荷注入，偏移和电容器失配引起的误差。电容器失配的程度通过每个待校准阶段的测量顺序确定。在进行测量之后，将值存储在存储器件中，以便在后续转换期间使用以消除由于偏移和电容器失配引起的误差。

3. 发明申请

WO1994026034A1 PROCESS FOR COMPENSATING COMPONENT TOLERANCES IN ANALOG-DIGITAL CONVERTERS 审中-公开
标题翻译：方法对于组件容忍的模拟 - 数字转换补偿
公开(公告)号：WO1994026034A1
公开(公告)日：1994-11-10
申请号：PCT/DE1994000408
申请日：1994-04-13
申请人： ROBERT BOSCH GMBH , TENTEN, Wilfried , BOEHL, Eberhard , GANGEI, Arnd
发明人： ROBERT BOSCH GMBH
IPC分类号： H03M01/10
CPC分类号： H03M1/1033 , H03M1/468 , H03M1/804
摘要： The proposal is for a process for compensating component tolerances of a series of similar components, especially capacitors (C1a to C8) in analog-digital converters which are connected to a shared line and the electrical value of which is halved from one component to another, in which the lowest-value component (C1a, C1b) is doubled. In this process, a first potential (Vdd) is first applied to at least one of the components (C8) and a second potential (Vss) is applied to the other lower-value components (C1a to C7). A comparator (12) then checks whether the median potential (Vm) between the two potentials (Vdd, Vss) is present on the shared line (16). To a correcting component (Ck) also connected to the shared line (16) is then applied a variable correcting voltage (Vk) which is tuned until the comparator (12) finds the median potential (Vm) on the shared line (16). Finally, the correcting voltage (Vm) so found is stored as a correcting value. It is thus possible to tune each of these components individually and compensate tolerance errors so that individual subsequent calibrations can be made which only very briefly interrupt the conversion operation of the analog-digital converter. The precision and linearity of an analog-digital converter fitted with such a tuned capacitor array are very great.

4. 发明申请

WO1995032552A1 REFERENCE LADDER AUTO-CALIBRATION CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER 审中-公开
标题翻译：用于模拟数字转换器的参考梯形图自动校准电路
公开(公告)号：WO1995032552A1
公开(公告)日：1995-11-30
申请号：PCT/US1995006135
申请日：1995-05-19
申请人： DAVID SARNOFF RESEARCH CENTER, INC.
发明人： DAVID SARNOFF RESEARCH CENTER, INC. , SAUER, Donald, J.
IPC分类号： H03M01/10
CPC分类号： H03M1/1004 , H03M1/365
摘要： An auto-calibrated reference resistor ladder network (140) is disclosed which is suitable for use in a precision ADC (110). Resistors in the ladder are connected to an auto-calibration circuit which continually measures the potential developed across each of the connected resistors and adjusts the resistance of the resistor to match the measured potential to a reference potential. The reference potential is the potential developed across a defined one of the resistors.
摘要翻译：公开了一种适用于精密ADC（110）的自动校准参考电阻梯形网络（140）。梯形电阻器连接到自动校准电路，该电路连续测量每个连接的电阻器上产生的电位，并调整电阻器的电阻以将测量电位与参考电位相匹配。参考电位是在限定的一个电阻器中产生的电位。

5. 发明申请

WO1991011056A1 METHOD AND DEVICE FOR ADJUSTMENT OF PHOTOELECTRIC CONVERTER OF SHAFT ROTATION ANGLE INTO CODE 审中-公开
标题翻译：用于调整轴转角的光电转换器的方法和装置
公开(公告)号：WO1991011056A1
公开(公告)日：1991-07-25
申请号：PCT/SU1990000017
申请日：1990-01-18
申请人： SPETSIALNOE KONSTRUKTORSKOE BJURO ...
发明人： SPETSIALNOE KONSTRUKTORSKOE BJURO ... , BABAIAN, Slava Khudanovich , SARKISIAN, Robert Ashotovich
IPC分类号： H03M01/10
CPC分类号： H03M1/1066 , H03M1/301
摘要： The essence of the invention consists in that first a preliminary adjustment of a measuring disk and an indicating disk (9, 2) is effected while turning the indicating disk (2) about the rotation axis of the shaft (4). On final adjustment of the measuring disk (9), two areas of its coding path (10) located at an angle ( alpha 1) are illuminated by means of illuminators (13), the bisector vector of the angle ( alpha 1) is determined and, while continuously turning the measuring disk (9) electric signals (18, 19) are generated by means of reading elements (15, 16), one of them being used as a reference signal and the other as a measuring signal. The eccentricity (e) of the path (10) is determined from the extreme values of the variable component of the phase difference ( DELTA phi ) of the signals (18, 19), and the moment of coincidence of the eccentricity vector and the bisector vector of the angle ( alpha 1) is determined from the change of sign and direction of said variable component. The disk (9) is moved by means of a mechanism (11) in a direction opposite to vector (e &cir& NOt ) until the variable component of the phase difference ( DELTA phi ) equals zero. On final adjustment of the indicating disk (2) another area of the path (10) is illuminated, the adjusted disk (9) is turned and an additional electric signal (21) is generated. The deviations from the calculated value of the phase difference ( DELTA phi ) between the reference and measuring signals and between the reference and additional signals (18, 19, 21) are determined. Then the disk (2) is moved by means of the mechanism (6) until the deviations of the phase difference ( DELTA phi ) equal zero.
摘要翻译：本发明的实质在于，首先在围绕轴（4）的旋转轴线转动指示盘（2）的同时，进行测量盘和指示盘（9,2）的初步调整。在测量盘（9）的最终调整中，通过照明器（13）照射其位于角度（α1）的编码路径（10）的两个区域，确定角度（α1）的二等分矢量并且在连续地转动测量盘（9）的同时，借助于读取元件（15,16）生成电信号（18,19），其中一个被用作参考信号，另一个用作测量信号。路径（10）的偏心率（e）根据信号（18,19）的相位差（DELTA phi）的可变分量的极值和偏心矢量与平分线的一致矩确定根据所述可变分量的符号和方向的变化来确定角度（α1）的矢量。盘（9）通过机构（11）沿与向量（e＆cir＆NOt）相反的方向移动，直到相位差（DELTA phi）的可变分量等于零。在指示盘（2）的最终调整中，路径（10）的另一个区域被照亮，调整后的盘（9）被转动并产生附加的电信号（21）。确定参考和测量信号之间以及参考和附加信号（18,19,21）之间的相位差（DELTA phi）的计算值的偏差。然后通过机构（6）使盘（2）移动，直到相位差（DELTA phi）的偏差等于零。

6. 发明申请

WO1989011757A1 SUBRANGING ANALOG-TO-DIGITAL CONVERTER WITH CALIBRATION 审中-公开
标题翻译：用校准模拟数字转换器
公开(公告)号：WO1989011757A1
公开(公告)日：1989-11-30
申请号：PCT/US1989001922
申请日：1989-05-05
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , MYERS, Terrence, L.
IPC分类号： H03M01/10
CPC分类号： H03M1/1042 , H03M1/164
摘要： A subranging analog-to-digital converter circuit (11) is disclosed which incorporates adaptive error correction for a high accuracy digitization of analog input signals. In a subranging analog-to-digital converter, a test circuit (41) for generating a series of digital test signals is provided. Included with the test circuit is a highly accurate, digital-to-analog converter (43) for converting the digital test signals to a respective series of accurate analog test signals for input to the subranging converter. The digital test signals are compared (47) with the respective outputs of the least significant bit quantizer of the subranging A/D converter, and correction signals for each subrange are stored in a memory storage means (49). The memory storage means (49) is addressed to provide the respective correction signal by signals from the MSB quantizer (17). In one embodiment, at least one test signal, preferably at mid-range, is used for each subrange. In another embodiment, numerous test signals for each subrange are used.
摘要翻译：公开了一种包括模拟输入信号的高精度数字化的自适应误差校正的子模拟 - 数字转换器电路（11）。提供了一种用于产生一系列数字测试信号的测试电路（41），在一个次级模拟 - 数字转换器中。包括在测试电路中的是一种高精度的数模转换器（43），用于将数字测试信号转换成各自的一系列准确的模拟测试信号，以输入到次级转换器。将数字测试信号与次级A / D转换器的最低有效位量化器的相应输出进行比较（47），并将每个子范围的校正信号存储在存储器存储装置（49）中。存储器存储装置（49）被寻址以通过来自MSB量化器（17）的信号提供相应的校正信号。在一个实施例中，对于每个子范围使用至少一个测试信号，优选在中间范围。在另一个实施例中，使用每个子范围的许多测试信号。

7. 发明申请

WO1997049188A1 METHOD OF TESTING AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：测试模拟数字转换器的方法
公开(公告)号：WO1997049188A1
公开(公告)日：1997-12-24
申请号：PCT/IB1997000611
申请日：1997-05-28
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , DE VRIES, Ronald , ATZEMA, Botjo
IPC分类号： H03M01/10
CPC分类号： H03M1/109 , H03M1/12
摘要： Only the value of the least-significant bit, or of some of the less-significant bits is used in order to test an analog-to-digital converter in an integrated circuit. The information concerning the differential and the integral non-linearity can be determined from the values of said less-significant bit. Furthermore, the functionality of the analog-to-digital converter is tested by counting the number of changes of the least-significant bit and by comparing this number with the value formed by the other bits.
摘要翻译：为了测试集成电路中的模数转换器，仅使用最低有效位或一些较低有效位的值。关于差分和积分非线性的信息可以从所述较低有效位的值确定。此外，模数转换器的功能通过对最低有效位的改变数进行计数并将其与其它位形成的值进行比较来测试。

8. 发明申请

WO1991007017A1 ANALOGUE TO DIGITAL CONVERTER 审中-公开
标题翻译：数字转换器的模拟
公开(公告)号：WO1991007017A1
公开(公告)日：1991-05-16
申请号：PCT/GB1990001686
申请日：1990-11-02
申请人： PLESSEY OVERSEAS LIMITED , LESLIE, Thomas, Coutts
发明人： PLESSEY OVERSEAS LIMITED
IPC分类号： H03M01/10
CPC分类号： H03M3/388 , H03M3/424
摘要： An analogue to digital converter circuit of the kind including an n-bit quantiser (where n > 1) for providing an output signal comprising an n-bit representation of the signal applied to its input, in which the quantiser is replaced by a quantiser element (3) providing an address location and a random access memory (RAM) device (4) at which an accurate representation of the corresponding output signal is stored, thus providing an instantaneous output signal of a predetermined level accuracy.

9. 发明申请

WO1990012459A1 ANALOG TO DIGITAL CONVERTER 审中-公开
标题翻译：模拟到数字转换器
公开(公告)号：WO1990012459A1
公开(公告)日：1990-10-18
申请号：PCT/US1990001466
申请日：1990-03-21
申请人： DIGITAL APPLIANCE CONTROLS, INC.
发明人： DIGITAL APPLIANCE CONTROLS, INC. , LODA, Michael, A.
IPC分类号： H03M01/10
CPC分类号： H03M1/50 , H03M1/18
摘要： There is provided herein a microprocessor based circuit including a capacitor charging circuit incorporating, in a first configuration, a varying resistance (RS) to be measured. In a second configuration the varying resistance (RS) is switched out of the circuit. In either configuration the timing capacitor (CT) is allowed to charge until a microcomputer logic level is reached. During that charge interval a counter runs on the clock cycles to generate a digital representation of the interval and therefor of the RC constant. Operation of the circuit in the second configuration, absent the varying resistance, produces a "zero" calibration for the circuit. Operation in the first configuration yields a representation of the varying resistance. Range sensitivity is accomplished by switching additional resistance (R1, R2...RN) into (or out of) the circuit to change the charging time of the capacitor.
摘要翻译：这里提供了一种基于微处理器的电路，其包括在第一配置中并入待测量的变化电阻（RS）的电容器充电电路。在第二配置中，变化电阻（RS）被切换出电路。在任一配置中，允许定时电容器（CT）充电直到达到微计算机逻辑电平。在该充电间隔期间，计数器在时钟周期上运行以产生间隔的数字表示，并且由此产生RC常数。电路的运行在第二种配置中，不存在变化的电阻，为电路产生“零”校准。在第一配置中的操作产生变化电阻的表示。范围灵敏度是通过将附加电阻（R1，R2 ... RN）切换到（或从）电路来实现的，以改变电容器的充电时间。

10. 发明申请

WO1998017003A3 TESTING CONTROL SIGNALS IN A/D CONVERTERS 审中-公开
公开(公告)号：WO1998017003A3
公开(公告)日：1998-04-23
申请号：PCT/IB1997001076
申请日：1997-09-08
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , SACHDEV, Manoj
IPC分类号： H03M01/10

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