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1. 发明申请

US20040246031A1 Ultra-low power programmable timer and low voltage detection circuits 有权
标题翻译：超低功耗可编程定时器和低电压检测电路
公开(公告)号：US20040246031A1
公开(公告)日：2004-12-09
申请号：US10764919
申请日：2004-01-26
申请人： Microchip Technology Incorporated
发明人： Ruan Lourens , Miguel Moreno
IPC分类号： H03K005/153
CPC分类号： G01K3/005 , G01K2215/00 , G01R19/16542 , G01R31/3648 , H03K5/06 , H03K5/08
摘要： An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes. Temperature may be determined from either a trip voltage compared to a known voltage determined at a known temperature, or a current value of the current source compared to a known current value determined at a known temperature, times a constant.
摘要翻译：在设备的数字集成电路中实现超低功率电压检测电路，以使用数字集成电路器件的单个连接和无源部件提供基本定时器，可编程定时器和可编程低电压检测（PLVD）在数字集成电路设备外部。可以使能内部低电流源，以便连接到输出连接的外部定时电容器放电，从而不需要外部电阻器。然而，通过添加外部放电电阻器和/或充电电阻器可以提高定时精度。输出连接可以被配置为三态输出，并且可以被驱动为高电荷并且使得定时电容器放电低。电压参考可用于确定用于定时和低电压检测目的的电压跳变点。温度可以由与在已知温度下确定的已知电压相比的跳闸电压或电流源的电流值与在已知温度下确定的已知电流值乘以常数来确定。

2. 发明申请

US20040245979A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20040245979A1
公开(公告)日：2004-12-09
申请号：US10844320
申请日：2004-05-13
发明人： Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
IPC分类号： H03K005/153
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit is provided with a reference voltage generation circuit for generating a voltage to be a reference, a function circuit that is operated using an output voltage of the reference voltage generation circuit, and a reference voltage stabilization capacitor for stabilizing the output voltage, which is connected to an output terminal of the reference voltage generation circuit. During standby, the function circuit stops operating while the reference voltage generation circuit continues operating to prevent discharging of the reference voltage stabilization capacitor, thereby realizing reduction in power consumption of the function circuit such as an analog circuit as well as high-speed recovery from the standby state to the normal operation state.
摘要翻译：半导体集成电路设置有用于产生作为基准的电压的基准电压产生电路，使用参考电压产生电路的输出电压进行操作的功能电路和用于稳定输出电压的基准电压稳定电容器，其连接到参考电压产生电路的输出端子。在待机期间，功能电路在参考电压产生电路继续工作时停止工作，以防止参考稳压电容器的放电，从而实现诸如模拟电路的功能电路的功耗降低以及来自待机状态为正常运行状态。

3. 发明申请

US20040232895A1 LOW NOISE FAST STABLE VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：低噪声快速稳定电压调节器电路
公开(公告)号：US20040232895A1
公开(公告)日：2004-11-25
申请号：US10709636
申请日：2004-05-19
发明人： Chi-Kun Chiu , Chi-Ming Hsiao
IPC分类号： H03K005/153
CPC分类号： G05F1/56
摘要： A low noise voltage regulator circuit with fast stable output voltage is disclosed. The low noise voltage regulator circuit contains a reference voltage generator, for generating a reference voltage; a switching circuit, which is electrically coupled to the output of reference voltage generator and has two states; and a stabilizing circuit. When the switching circuit is at a first state, the reference voltage is coupled to the stabilizing circuit without being filtered; when the switching circuit is at a second state, the reference voltage is filtered by a low pass filter before being coupled to the stabilizing circuit. A switching control signal is used to switch the switching circuit between the two states. The filtered reference voltage is used to generate a low noise regulated output voltage.
摘要翻译：公开了一种具有快速稳定输出电压的低噪声稳压电路。低噪声稳压器电路包含用于产生参考电压的参考电压发生器; 开关电路，其电耦合到参考电压发生器的输出并具有两种状态; 和稳定电路。当开关电路处于第一状态时，参考电压被耦合到稳定电路而不被滤波; 当开关电路处于第二状态时，在耦合到稳定电路之前，参考电压被低通滤波器滤波。开关控制信号用于在两种状态之间切换开关电路。滤波后的参考电压用于产生低噪声调节输出电压。

4. 发明申请

US20040174757A1 Content addressable control system 失效
标题翻译：内容可寻址控制系统
公开(公告)号：US20040174757A1
公开(公告)日：2004-09-09
申请号：US10800231
申请日：2004-03-12
发明人： Steven L. Garverick , Michael L. Nagy
IPC分类号： H03K005/153
CPC分类号： G02B6/357 , G02B6/266 , G02B6/3512 , G02B6/3518 , G02B6/3556 , G02B6/356 , G02B26/0841 , G02B2006/12104 , H04Q11/0005 , H04Q2011/0022 , H04Q2011/0024 , H04Q2011/003 , H04Q2011/0039 , H04Q2011/0049
摘要： Pulse-width modulation (PWM) control and drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. The high-voltage portion may be incorporated in an integrated circuit having drive cells vertically aligned with the MEMS elements. A control cell associated with each actuator includes a register selectively stored with a desired pulse width. A clocked counter distributes its outputs to all control cells. When the counter matches the register, a polarity signal corresponding to a drive clock is latched and controls the voltage applied to the electrostatic cell. The MEMS element may be a tiltable plate supported in its middle by a torsion beam. Complementary binary signals may drive two capacitors formed across the axis of the beam. The register and comparison logic for each cell may be formed by a content addressable memory.
摘要翻译：脉冲宽度调制（PWM）控制和驱动电路特别适用于微机电系统（MEMS）中形成的静电致动器阵列，例如用于光开关。高压部分可以结合在具有与MEMS元件垂直对准的驱动单元的集成电路中。与每个致动器相关联的控制单元包括选择性地以期望的脉冲宽度存储的寄存器。时钟计数器将其输出分配给所有控制单元。当计数器与寄存器匹配时，锁存与驱动时钟对应的极性信号，并控制施加到静电电池的电压。 MEMS元件可以是通过扭转梁在其中间支撑的可倾斜板。互补的二进制信号可以驱动跨过光束的轴形成的两个电容器。每个单元的寄存器和比较逻辑可以由内容可寻址存储器形成。

5. 发明申请

US20040145405A1 ANALOG FLOATING GATE VOLTAGE SENSE DURING DUAL CONDUCTION PROGRAMMING 有权
标题翻译：双向导通编程期间模拟浮动门电压检测
公开(公告)号：US20040145405A1
公开(公告)日：2004-07-29
申请号：US10353404
申请日：2003-01-28
发明人： William H. Owen
IPC分类号： H03K005/153
CPC分类号： H03K5/2481 , G11C16/0441 , G11C16/3468 , G11C27/005 , H03K5/249
摘要： A method for sensing the voltage on a floating gate in a floating gate circuit during a set mode is disclosed. The method includes the steps of: a) causing the floating gate circuit to enter into a set mode, wherein a first predetermined voltage is coupled to the gate of a second transistor in the floating gate circuit; b) causing the voltage on the floating gate to be sensed relative to the first voltage by a first transistor; c) causing an output voltage to be generated by the floating gate circuit; and d) causing the voltage on the floating gate to be modified as a function of the output voltage, including modifying the charge level on said floating gate under the control of a first tunnel device and a second tunnel device operating in dual conduction during said set mode, said first tunnel device formed between said floating gate and a first tunnel electrode and said second tunnel device formed between said floating gate and a second tunnel electrode; and e) repeating steps b) through d) until the voltage on the floating gate is approximately equal to the first voltage.
摘要翻译：公开了一种用于在设定模式期间感测浮置栅极电路中的电压的方法。该方法包括以下步骤：a）使浮置栅极电路进入设定模式，其中第一预定电压耦合到浮置栅极电路中的第二晶体管的栅极; b）通过第一晶体管使相对于第一电压感测浮栅上的电压; c）使浮栅电路产生输出电压; 以及d）使浮动栅极上的电压作为输出电压的函数被修改，包括在第一隧道装置的控制下修改所述浮动栅极上的电荷电平，以及在所述集合期间在双重导通中工作的第二隧道装置所述第一隧道装置形成在所述浮栅和第一隧道电极之间，所述第二隧道装置形成在所述浮栅和第二隧道电极之间; 和e）重复步骤b）至d），直到浮栅上的电压近似等于第一电压。

6. 发明申请

US20040130355A1 High-voltage detecting circuit 失效
公开(公告)号：US20040130355A1
公开(公告)日：2004-07-08
申请号：US10673226
申请日：2003-09-30
申请人： Oki Electric Industry Co., Ltd.
发明人： Kazuhiko Oyama
IPC分类号： H03K005/153
CPC分类号： H03K5/153 , G01R19/16519 , G01R31/31701
摘要： As a power-supply voltage VCC is applied to a second terminal, a latch is reset by a reset signal POR from a power-on reset unit. Subsequently, as the voltage of a signal IN applied to a first terminal is increased to higher than the voltage VCC by a threshold voltage Vth of a PMOS 11, the PMOS 11 turns on, causing a node N1 to become nullH.null Thus, a test mode is set in the latch. Subsequently, even if the signal IN is reduced to VCC or lower, the test mode is maintained. A high-voltage test can be conducted by increasing the power-supply voltage at the second terminal, thereby eliminating the need for applying the first terminal with a higher voltage than required to set the test mode. It is therefore possible to prevent a gate oxide film of a buffer from being destroyed.

7. 发明申请

US20040113662A1 Presence indication signal associated with an attachment 有权
标题翻译：与附件相关联的存在指示信号
公开(公告)号：US20040113662A1
公开(公告)日：2004-06-17
申请号：US10316373
申请日：2002-12-11
发明人： Knut S. Grimsrud
IPC分类号： H03K005/153
CPC分类号： G06F13/409
摘要： According to some embodiments, a presence indication associated with an attachment is provided.
摘要翻译：根据一些实施例，提供与附件相关联的存在指示。

8. 发明申请

US20030062928A1 High speed peak amplitude comparator 有权
标题翻译：高速峰值振幅比较器
公开(公告)号：US20030062928A1
公开(公告)日：2003-04-03
申请号：US09969837
申请日：2001-10-01
发明人： Afshin Momtaz , Wee-Guan Tan , Armond Hairapetian
IPC分类号： H03K005/153
CPC分类号： H03K5/1532 , G01R19/04
摘要： Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.
摘要翻译：用于实现高速峰值幅度比较的各种方法和电路。本发明通过消除峰值检测中通常使用的慢反馈环路来实现更高的操作速度。在一个实施例中，本发明直接将表示输入信号的峰值振幅减去较小电压降的信号与修改的参考电压进行比较。修改的参考电压对应于调整为补偿最大输入电压中的小电压降的参考电压。在另一个实施例中，本发明实现了峰值振幅比较器的差分版本，以获得更好的噪声抑制和降低的有效偏移等优点。

9. 发明申请

US20020167342A1 Signal reception circuit, data transfer control device and electronic equipment 有权
标题翻译：信号接收电路，数据传输控制装置及电子设备
公开(公告)号：US20020167342A1
公开(公告)日：2002-11-14
申请号：US10142333
申请日：2002-05-10
申请人： SEIKO EPSON CORPORATION
发明人： Akira Nakada
IPC分类号： H03K005/153
CPC分类号： H03K5/1532 , H03K5/082
摘要： A signal reception circuit capable of detecting and receiving a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. A differential pair of reception signals DP and DM is detected by an HS_SQ_L circuit for low speed having high receiving sensitivity and an HS_SQ circuit for high speed having high speed response performance. In the case of a high-speed reception signal, a logical product of a signal HS_DataIn fetched by an HS differential data receiver and a signal HS_SQ indicating the result of signal detection by the HS_SQ circuit for high speed is supplied to a DLL circuit. In the case of a low-speed reception signal, an FS differential receiver is activated after the detection of differential pair of reception signals DP and DM by the HS_SQ_L circuit for low speed. A signal FS_DataIn fetched by the FS differential receiver is supplied to an FS circuit.
摘要翻译：能够检测和接收具有小幅度的高速信号的信号接收电路，以及使用该信号的数据传送控制装置和使用该信号的电子设备。接收信号DP和DM的差分对通过具有高接收灵敏度的低速HS_SQ_L电路和具有高速响应性能的高速HS_SQ电路来检测。在高速接收信号的情况下，将通过HS差分数据接收器取出的信号HS_DataIn和表示HS_SQ电路的高速信号检测结果的信号HS_SQ的逻辑积提供给DLL电路。在低速接收信号的情况下，通过HS_SQ_L电路对差分接收信号DP和DM进行低速检测后，FS差分接收器被激活。由FS差分接收器取出的信号FS_DataIn被提供给FS电路。

10. 发明申请

US20020163364A1 Power supply detection device 有权
标题翻译：电源检测装置
公开(公告)号：US20020163364A1
公开(公告)日：2002-11-07
申请号：US10113859
申请日：2002-04-01
申请人： STMicroelectronics S.A.
发明人： Sylvain Majcherczak , Guy Mabboux
IPC分类号： H03K005/153
CPC分类号： H03K17/302 , H03K17/223 , H03K19/0016 , H03K19/007
摘要： In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.
摘要翻译：在集成电路中，检测装置检测集成电路的磁芯的电源电压的下降或相对于集成电路的输入/输出接口电路的电源电压过度缓慢的累积。通过检测装置将接口电路的输出设置为高阻抗状态，以最小化其功耗。

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