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1. 发明申请

WO1998015891A1 APPARATUS AND METHOD FOR CONVERTING DIGITAL WORDS OR BYTES OF A GIVEN NUMBER OF BITS TO BYTES OF A DIFFERENT NUMBER OF BITS 审中-公开
标题翻译：将数字数字或字数转换为不同位数字节的装置和方法
公开(公告)号：WO1998015891A1
公开(公告)日：1998-04-16
申请号：PCT/US1997017763
申请日：1997-10-02
申请人： ASCOM TIMEPLEX TRADING AG , SCARANGELLA, Anthony, T.
发明人： ASCOM TIMEPLEX TRADING AG , ROJAS, Alfonso, R.
IPC分类号： G06F05/00
CPC分类号： G06F5/00
摘要： Apparatus (60; 220; 600; 800; 1000) and method (70; 300; 500; 700; 900) are provided for converting, at high speed, without queuing of data, and with absolute accuracy, parallel bytes of digital data having a given number of binary bits as employed by one class of equipment to parallel bytes having a different (greater or smaller) number of bits as employed by another class of equipment. Such conversion is necessary in order to make possible unimpeded communication between the two classes of equipment. Converting of bytes is accomplished by momentarily storing as current data and as remainder data respective bits of successive incoming bytes clock count by clock count (70; 300; 500; 700; 900); identifying within each count a desired number of bits stored as remainder data, or current data, or both and grouping them into a set of bits to be outputted as an outgoing byte during a respective count; outputting such sets of bits clock count by clock count as outgoing bytes such that the outgoing bytes each have a different number of bits versus the number of bits in each incoming byte, and the outgoing bits have a desired numerical sequence; and periodically compensating (1/2 count; NOP, EOP) for the total number of bits outputted versus the number inputted during a given period of time.
摘要翻译：提供了装置（60; 220; 600; 800; 1000）和方法（70; 300; 500; 700; 900），用于高速转换，不排队数据，绝对准确地，具有数字数据的并行字节，给定数量的二进制位由一类设备用于具有由另一类设备使用的不同（更大或更小）位数的并行字节。这样的转换是必要的，以便使两种设备之间可能无阻碍地进行通信。字节转换是通过将时钟计数（70; 300; 500; 700; 900）暂时存储为当前数据和作为连续输入字节时钟计数的剩余数据的相应位来实现的。在每个计数内识别作为余数数据或当前数据存储的所需数量的位，或两者，并将它们分组为在相应计数期间作为输出字节输出的一组位; 通过时钟计数作为输出字节输出这样的位组时钟计数，使得输出字节各自具有与每个输入字节中的位数不同的位数，并且输出位具有期望的数字序列; 并且对于输出的总位数与给定时段期间输入的数量周期性地补偿（1/2计数; NOP，EOP）。

2. 发明申请

WO1991013395A1 DATA COMPRESSION AND RESTORATION METHOD AND DEVICE THEREFOR 审中-公开
标题翻译：数据压缩和恢复方法及其设备
公开(公告)号：WO1991013395A1
公开(公告)日：1991-09-05
申请号：PCT/JP1991000252
申请日：1991-02-26
申请人： FUJITSU LIMITED , YOSHIDA, Shigeru , NAKANO, Yasuhiko , OKADA, Yoshiyuki , CHIBA, Hirotaka
发明人： FUJITSU LIMITED
IPC分类号： G06F05/00
CPC分类号： G06T9/005 , H03M7/3088
摘要： A data compression and restoration device which reads out a fed character string one character at a time and holds a present character substring being the coding object, and which refers to a character substring of maximum length matching with the present character substring from among the character substrings registered in the dictionary according to the relation to the last character of the preceding character substring and codes the longest match character part. The device also gives one new reference number to the present character substring which is generated newly by adding the next character to the longest match character string, and codes the same by registering it in the dictionary. The character substring registered in the dictionary by the code expressed by the reference number of the character substring is retrieved to restore the original character substring, and a new reference number is given to a character substring comprising a restored character string and the first character of the character string to be decoded next while decoding the character string by registering it in the dictionary. Thereby, the compressibility of data coding is improved.

3. 发明公开

EP0097834A3 Circuits for accessing a variable width data bus with a variable width data field 失效
标题翻译：用于访问具有可变宽度数据字段的可变宽度数据总线的电路
公开(公告)号：EP0097834A3
公开(公告)日：1987-02-25
申请号：EP83105439
申请日：1983-06-01
申请人： International Business Machines Corporation
发明人： Dill, Frederick Hayes , Ling, Daniel Tajen , Matick, Richard Edward , McBride, Dennis Jay
IPC分类号： G06F05/00
CPC分类号： G06F7/764 , G06F5/00 , G06F5/01 , G06F13/4018
摘要： A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N c and a data field of N f , the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. Structure includes a modulo N c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N c . A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.

4. 发明公开

EP0055126A3 High-speed byte shifting apparatus 有权
标题翻译：高速字节移位装置
公开(公告)号：EP0055126A3
公开(公告)日：1983-08-03
申请号：EP81306040
申请日：1981-12-22
申请人： SPERRY CORPORATION
发明人： O'Brien, Steven Michael
IPC分类号： G06F05/00
CPC分类号： G06F11/10 , G06F5/01
摘要： Byte shifting apparatus for high speed bus architecture data processing systems comprises a plurality of byte shifters (14, 15, 16, 17), one for each byte, each with a corresponding number of input ports (e.g. 18, 19, 20, 22) and an output port (18). Data are read from the bus (13) into each byte shifter through one of its input ports selected by shift control means (37) and are returned to the bus through its output port. Fill logic (56) is provided for filling bytes with ones or zeros as required before returning them to the bus. Checking means, not shown in Figure 1, are provided within each byte shifter for checking bit parity, shift error, shift select error, and loading of the buffer register within the shifter with the shifted byte.

5. 发明公开

EP0047382A3 Adaptive compression encoding of a binary-source symbol string 失效
标题翻译：二进制符号字符串的自适应压缩编码
公开(公告)号：EP0047382A3
公开(公告)日：1982-10-13
申请号：EP81105735
申请日：1981-07-21
申请人： International Business Machines Corporation
发明人： Goertzel, Gerald
IPC分类号： G06F05/00
CPC分类号： H03M7/42
摘要： This invention relates to a technique for appending prefixed code words to a code word stream conditioned by each least probable symbol in a binary source symbol string. The generation of the prefixed code word from a bounded code word space is managed dynamically by a memory (9) requiring only space availability measures (47, 51) at the start and end of the encoding cycle as input thereto. The memory delivers the prefixed code word of an appropriate derived length to output devices (7) for further processing. The encoder (2), responsive to each input triplet of symbol, symbol estimate, and probability of occurrence measure, generates the space availability measures PC(i) and PC(i-I), and modifies the memory contents so as to reduce the remaining code space. This reduction reflects the fact that the particular code word delivered has been used up and cannot be the prefix of any future delivered code word. The length of each code word requested is composed of two components. The first is the «run» of most probable symbols component, and the second is the terminating least probable symbol component. When the code word length requested exceeds the capacity of the memory to deliver, then the code word length is decreased to the maximum permissible. When the code word space is used up, the memory is considered overflowed and results in a reset in which the code capacity is reinitialized.

6. 发明公开

EP0030635A3 Method and apparatus for generating complex characters 失效
标题翻译：用于产生复杂特征的方法和装置
公开(公告)号：EP0030635A3
公开(公告)日：1982-01-13
申请号：EP80107152
申请日：1980-11-18
申请人： International Business Machines Corporation
发明人： Goertzel, Gerald , Powell, Carl George , Tseng, Samuel Chin-Chong
IPC分类号： G09F01/02 , G06K15/10 , B41B19/00 , G06F05/00
CPC分类号： B41B19/01 , G06K15/10 , G06K2215/0028 , G09G5/246
摘要： A character compaction and generation method and apparatus which is particularly adapted to the generation of complex characters such as Kanji characters. A dot matrix (Fig. 2-1) defining a given character is compacted into a sparse matrix (Fig. 2-7), with the original character being reconstructed for printing or display from the compacted character defined in the sparse matrix. Each character in the complex character set is compacted and stored in memory (50) one time only, with decompaction being performed each time a given character is to be generated. A set of symbols are defined to represent different patterns which occur frequently in the entire complex character set. Different combinations of the symbols define a given character. The information stored for each sparse matrix representing a given character is comprised of eacn symbol in the sparse matrix, its position, and its size parameter if the symbol represents a family of patterns which differ only in size. Three groups (A, B, C,) of different patterns are defined which occur frequently in the complex character set, namely, a first group (A) which has a fixed size for each pattern, a second group (B) which has one size parameter which must be specified for each pattern, and a third group (Cl which has a plurality of size parameters which must be specified for each pattern. Certain ones of the characters have elements of different patterns which overlap, such that the character may be encoded utilizing less symbols, and according less bytes of data. A given pattern may be generated atthe same time another pattern is being decoded.
摘要翻译：一种字符压缩和生成方法和装置，其特别适用于生成诸如汉字字符的复杂字符。定义给定字符的点矩阵被压缩成稀疏矩阵，其中原始字符被重构用于从稀疏矩阵中定义的压缩字符进行打印或显示。复杂字符集中的每个字符都被压缩并存储在存储器中一次，每当要生成给定字符时执行解压缩。一组符号被定义为表示在整个复杂字符集中频繁出现的不同模式。符号的不同组合定义给定的字符。对于表示给定字符的每个稀疏矩阵存储的信息由稀疏矩阵，其位置和其大小参数中的每个符号组成，如果符号表示仅在大小上不同的模式族。定义了在组合字符集中频繁出现的三组不同的模式，即对于每个模式具有固定大小的第一组，具有必须为每个模式指定的一个大小参数的第二组，以及第三组其具有必须为每个模式指定的多个尺寸参数。

7. 发明公开

EP0164451A3 An arithmetic processing unit for executing a floating point operation 失效
标题翻译：用于执行浮点操作的算术处理单元
公开(公告)号：EP0164451A3
公开(公告)日：1988-11-17
申请号：EP84116332
申请日：1984-12-27
申请人： NEC CORPORATION
发明人： Tanaka, Hideo c/o NEC Corp.
IPC分类号： G06F05/00
CPC分类号： G06F7/485 , G06F7/49915
摘要： An arithmetic processing unit executes a first operation to adjust a scale of an exponent part of one data to that of the other data, a second operation to arithmetically calculate the mantissa parts of the two data according to a desired arithmetic operation, and a third operation to correct the exponent part according to the result of the calculation. A proposed arithmetic unit includes an incrementer to increase the exponent part by +1 in parallel with the calculating operation without respect to the overflow and a selector to select the output of the incrementer according to the result of the calculation. Therefore, these three operations can be performed at a high speed in only two cycles.

8. 发明公开

EP0130413A3 A multi-stage pass transistor shifter/rotator 失效
标题翻译：多级通道转换器/旋转器
公开(公告)号：EP0130413A3
公开(公告)日：1988-11-17
申请号：EP84106532
申请日：1984-06-08
申请人： International Business Machines Corporation
发明人： Chappell, Barbara Alane , Hsieh, Hung-Hui
IPC分类号： G06F05/00
CPC分类号： G06F5/015 , G11C19/38
摘要： A digital shifter/rotator (1000) for shifting an input word by an amount depending on a shift control word (4000) is described. The shifter/rotator comprises an array of FET pass transistors arranged in a sequential number of stages (1200, 1400, 1600, 1700, 1800). The amount to be shifted in each stage is controlled by a corresponding shift control bit on lines 4200 of the shift control word buffered by drivers 4500, whereby the output word of the rotator is the input word shifted by an amount equal to a sum of the number of shifts effected in each of the stages as determined by the shift control word. The rotator features selectable amount of shift in one machine cycle, high performance and reduced device count. Further improved performance is obtained by utilizing decoupling devices for isolating the input points of the stages, except when providing rotation, from the long rotation cross buses and its associated large parasiticcapac- itances.

9. 发明公开

EP0127815A3 Data compression method 失效
标题翻译：数据压缩方法
公开(公告)号：EP0127815A3
公开(公告)日：1988-07-27
申请号：EP84105546
申请日：1984-05-16
申请人： International Business Machines Corporation
发明人： Miller, Victor Saul , Wegman, Mark N.
IPC分类号： G06F05/00
CPC分类号： H03M7/3088 , G06T9/005
摘要： Communications between a Host Computing System and a number of remote terminals is enhanced by a data compression method which modifies the data compression method of Lempel and Ziv by addition of new character and new string extensions to improve the compression ratio, and a least recently used routine to limit the encoding tables to a fixed size to significantly improve data transmission efficiency.

10. 发明公开

EP0163209A3 Display architecture having variable data width 失效
标题翻译：具有可变数据宽度的显示架构
公开(公告)号：EP0163209A3
公开(公告)日：1987-02-04
申请号：EP85106035
申请日：1985-05-17
申请人： International Business Machines Corporation
发明人： Matick, Richard Edward , Ling, Daniel Tajen , Dill, Frederick Hayes
IPC分类号： G06F05/00
CPC分类号： G09G5/391 , G06F5/01 , G09G5/39
摘要： The display architecture supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X o , Y o , the data path width No and an encoded segment width S. bit incrementer in the function generator generates A increment bits A l based on the externally supplied modulo No. The function generator generates the physical word address W o and physical bit address b o based on the starting address X o , Y o , the data path width No and the encoded segment width S. Logic circuitry is responsive to an overflow bit produced by the bit incrementer to control spill and wrap function.

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