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1. 发明授权

US06535024B1 Clock signal filtering circuit 有权
标题翻译：时钟信号滤波电路
公开(公告)号：US06535024B1
公开(公告)日：2003-03-18
申请号：US09399233
申请日：1999-09-17
申请人： Laurent Rochard
发明人： Laurent Rochard
IPC分类号： G01R2902
CPC分类号： H03K5/156
摘要： A clock signal filtering circuit includes a bistable flip-flop and a controller for controlling state changes of the flip-flop. A first activation circuit activates the controller by edges of non-filtered clock signal pulses when their duration exceeds a first threshold. The first threshold is equal to a half-period corresponding to an upper frequency limit of the clock signal. A second activation circuit activates the controller by edges of filtered clock signal pulses delayed by an amount equal to a half period corresponding to a lower frequency limit of the clock signal. The clock filtering circuit transmits a filtered clock signal at a frequency within a specification interval, and at a duty cycle equal to 0.5 for a variety of different circumstances.
摘要翻译：时钟信号滤波电路包括双稳态触发器和控制器，用于控制触发器的状态变化。当其持续时间超过第一阈值时，第一激活电路通过非滤波时钟信号脉冲的边缘激活控制器。第一阈值等于对应于时钟信号的上限频率的半周期。第二激活电路通过延迟等于对应于时钟信号的较低频率限制的半周期的量的滤波时钟信号脉冲的边沿来激活控制器。时钟滤波电路以规定间隔内的频率发送经滤波的时钟信号，并且在各种不同情况下以等于0.5的占空比发送。

2. 发明授权

US06701269B1 Jitter measurement extrapolation and calibration for bit error ratio detection 失效
标题翻译：用于误码率检测的抖动测量外推和校准
公开(公告)号：US06701269B1
公开(公告)日：2004-03-02
申请号：US10352716
申请日：2003-01-28
申请人： Roger L. Jungerman , Lovell H. Camnitz
发明人： Roger L. Jungerman , Lovell H. Camnitz
IPC分类号： G01R2902
CPC分类号： G01R31/31709 , G01R29/26 , G01R31/3171 , G01R31/31725
摘要： Error-related information acquired using a bit error ratio detector (BERT) is extrapolated on the basis of prior testing, in which measurements “superior” to those acquired by the BERT are used to provide an initial extrapolation calibration. For example, measures of data dependent jitter acquired by a digital communications analyzer (DCA) may be used to offset the less accurate jitter-related measures by the BERT. As a consequence, the benefits of a DCA and a BERT are combined, while using only the BERT.
摘要翻译：使用误码率检测器（BERT）获取的误差相关信息是基于先前的测试进行外插的，其中使用由BERT获得的测量值“优于”提供初始外推校准。例如，可以使用由数字通信分析器（DCA）获取的依赖于数据的抖动的测量来抵消由BERT产生的不太准确的抖动相关措施。因此，组合DCA和BERT的优点，而仅使用BERT。

3. 发明授权

US06601004B2 Method and apparatus for measuring parameters of an electronic system 失效
标题翻译：用于测量电子系统参数的方法和装置
公开(公告)号：US06601004B2
公开(公告)日：2003-07-29
申请号：US09845197
申请日：2001-05-01
申请人： Alex Ballantyne , David Taylor
发明人： Alex Ballantyne , David Taylor
IPC分类号： G01R2902
CPC分类号： H04L1/24 , H04L1/205
摘要： Timing errors in digital transmission systems, such as maximum time interval error, are measured with data samples processed in a first stage to produce in real-time a first, time-varying series of measurements for a given parameter over observation intervals of a first magnitude. Each observation interval is many times longer than the sample period of the input series. Subsequent stages derive further measurements, corresponding to increasingly longer observation intervals, derived by treating previous observation intervals as sub-intervals. The first stage derives intermediate results for a predetermined interval and repeats for successive sub-intervals. The intermediate results are stored in a first first-in, first-out (FIFO) data set and updated at least once per sub-interval and the required parameter is derived. The second and subsequent stages similarly derive the required parameter corresponding to increasing observation interval magnitudes and update the measurements as data sets update.
摘要翻译：数字传输系统中的定时误差，例如最大时间间隔误差，用在第一阶段中处理的数据样本进行测量，以实时地产生一个给定参数的第一个时变系列的测量值，该测量值在第一幅度的观测间隔上。每个观察间隔比输入序列的采样周期多很多倍。后续阶段通过将先前的观察间隔视为子间隔而导出的对应于越来越长的观察间隔的进一步测量。第一阶段以预定间隔导出中间结果，并重复连续的子间隔。中间结果存储在第一先进先出（FIFO）数据集中，并且每个子间隔至少更新一次，并且导出所需参数。第二阶段和后续阶段类似地导出对应于增加的观测间隔幅度的所需参数，并且在数据集更新时更新测量。

4. 发明授权

US06549859B1 Method of time stamping a waveform edge of an input signal 失效
标题翻译：时间戳输入信号波形边缘的方法
公开(公告)号：US06549859B1
公开(公告)日：2003-04-15
申请号：US09654665
申请日：2000-09-05
申请人： Benjamin A. Ward
发明人： Benjamin A. Ward
IPC分类号： G01R2902
CPC分类号： G01R13/0245 , G01R13/0272 , G01R13/30 , G01R13/305 , G01R13/345 , G01R19/175
摘要： The time stamping method for an input signal generates time marked digital data values as a reference edge and defines at least a first time stamp in the reference edge. Digital data samples of the input signal are acquired to create a waveform record of the input signal. The digital data samples of a waveform record edge are compared to time equivalent digital data values of the reference edge to generate a error value representative of the difference between the waveform record edge and the reference edge. A time offset value is generated from the error value to vary the time location of the reference edge and the comparison and time offset generating steps are repeated to minimize the error value. The time offset value at the minimum error value is combined with a time location of nearest digital data sample of the waveform record edge to generate a waveform record edge time stamp.
摘要翻译：用于输入信号的时间戳方法生成时间标记的数字数据值作为参考边缘，并且在参考边缘中定义至少第一时间戳。获取输入信号的数字数据采样以产生输入信号的波形记录。将波形记录边缘的数字数据样本与参考边缘的时间等效数字数据值进行比较，以生成表示波形记录边缘和参考边缘之间的差异的误差值。从误差值产生时间偏移值以改变参考边缘的时间位置，并且重复比较和时间偏移生成步骤以最小化误差值。将最小误差值处的时间偏移值与波形记录边缘的最近数字数据采样的时间位置相组合，以生成波形记录边沿时间戳。

5. 发明授权

US06522986B1 Apparatus and method for testing processing circuit for joystick buttons 有权
标题翻译：用于测量操纵杆按钮的处理电路的装置和方法
公开(公告)号：US06522986B1
公开(公告)日：2003-02-18
申请号：US09632086
申请日：2000-08-02
申请人： Chia-Chin Chu , Wen-Lung Hsu
发明人： Chia-Chin Chu , Wen-Lung Hsu
IPC分类号： G01R2902
CPC分类号： G01R31/317 , G01R31/2829 , G01R31/31715
摘要： An apparatus for testing a main board processing circuit for joystick buttons. The apparatus is used for testing the processing circuit of a main board, wherein the processing circuit is coupled to the joystick through a connector. The apparatus contains a test tool and a short-circuit node, wherein the test tool contains M pins, corresponding to M pins of the connector, for coupling the test tool with the connector. N pins of the M pins of the test tool correspond to the N pins of the connector, which are connected to the buttons. The short-circuit node is the common node of the N pins that are all short-circuited for simulating the actions of the joystick buttons. In the test, the connector is firstly connected to the test tool and the status values stored in a status register are detected. The connection is then disconnected from the test tool.
摘要翻译：一种用于测试用于操纵杆按钮的主板处理电路的装置。该装置用于测试主板的处理电路，其中处理电路通过连接器耦合到操纵杆。该装置包含测试工具和短路节点，其中测试工具包含M个针脚，对应于连接器的M个引脚，用于将测试工具与连接器相连接。测试工具的M个引脚的N个引脚对应于连接器的N个引脚，连接到这些按钮。短路节点是N个引脚的公共节点，都是短路的，用于模拟操纵杆按钮的动作。在测试中，连接器首先连接到测试工具，并检测存储在状态寄存器中的状态值。然后将连接与测试工具断开连接。

6. 发明授权

US06687632B1 Testing of CATV systems 失效
标题翻译：有线电视系统测试
公开(公告)号：US06687632B1
公开(公告)日：2004-02-03
申请号：US09582561
申请日：2000-06-27
申请人： Daniel E. Rittman
发明人： Daniel E. Rittman
IPC分类号： G01R2902
CPC分类号： H04B3/46 , H04N17/00
摘要： A method and apparatus for determining the location of an impedance mismatch in a digital communication circuit (22) generate (20) at least quasi-random data, transmit the data along the circuit (22) from a transmitting end of the circuit (22), recover (24) reflections from impedance mismatches in the circuit (22) adjacent the transmitting end of the circuit (22), correlate the reflections with the data to generate a correlation result, identify a reflection peak in the result, and multiply the propagation velocity of the data through the circuit (22) by a time delay to the reflection peak.
摘要翻译：用于确定数字通信电路（22）中的阻抗失配位置的方法和装置产生至少准随机数据（20），从电路（22）的发送端沿着电路（22）发送数据，从邻近电路（22）的电路（22）的电路（22）的阻抗失配恢复（24）反射，将反射与数据相关联，以产生相关结果，识别结果中的反射峰值，并乘以传播数据通过电路（22）的时间延迟到反射峰值的速度。

7. 发明授权

US06507221B2 Circuit for the filtering of parasitic logic signals 有权
公开(公告)号：US06507221B2
公开(公告)日：2003-01-14
申请号：US09938289
申请日：2001-08-23
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G01R2902
CPC分类号： H03K5/1252
摘要： A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

8. 发明授权

US06484112B1 Method for estimating the frequency of a time signal 失效
标题翻译：估计时间信号频率的方法
公开(公告)号：US06484112B1
公开(公告)日：2002-11-19
申请号：US09600649
申请日：2000-07-20
申请人： Frank Scheppach
发明人： Frank Scheppach
IPC分类号： G01R2902
CPC分类号： G06F17/141 , G01R23/16
摘要： A method for estimating the frequency of a time signal by means of a discrete Fourrier transformation and interpolation between support points of the DFT spectrum. According to said method, the hamming window is used in a known manner for filter and the interpolation is carried out according to the mathematically calculated solution. The method makes use of the pact that a function of the third degree which can serve as correction distance has a clear solution within the definition range of the amount ration between a secondary maximum and a primary maximum of the DFT spectrum. The correction distance is calculated according to this solution on the basis of the ratio of the secondary maximum and the primary maximum.
摘要翻译：一种用于通过离散傅立叶变换和DFT频谱的支持点之间的插值来估计时间信号的频率的方法。根据所述方法，汉明窗以已知的方式用于滤波器，并且根据数学计算的解进行插值。该方法利用该协定，可以作为校正距离的第三度的函数在DFT频谱的次级最大值和初级最大值之间的量值的定义范围内具有清晰的解决方案。根据该解决方案根据二次最大值和一次最大值的比率计算校正距离。

9. 发明授权

US06249141B1 Enhanced glitch removal circuit 失效
标题翻译：增强毛刺去除电路
公开(公告)号：US06249141B1
公开(公告)日：2001-06-19
申请号：US09422261
申请日：1999-10-21
申请人： Reuben A. Aspacio , Rajesh Bharadwaj , Hieu Xuan Nguyen
发明人： Reuben A. Aspacio , Rajesh Bharadwaj , Hieu Xuan Nguyen
IPC分类号： G01R2902
CPC分类号： H03K5/1252
摘要： An enhanced glitch eater circuit for eliminating glitch signals occurring within a predetermined period from a raising edge or a falling edge of a signal pulse is comprised of an inverter connected to a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate receiving a latched signal at one input and a delay latched signal at the other input, the latched signal being from the output of the transmission gate. The latched signal may be reset by a transistor.
摘要翻译：用于消除从信号脉冲的上升沿或下降沿起的预定周期内发生的毛刺信号的增强型毛刺消除器电路包括连接到由双输入XNOR（异或）门在一个输入端接收锁存信号，在另一输入端接收延迟锁存信号，锁存信号来自传输门的输出。锁存信号可以由晶体管复位。

10. 发明授权

US06836738B2 Method for optimized rendering of eye diagrams synchronized to a recovered clock and based on a single shot acquisition 有权
标题翻译：用于优化与恢复的时钟同步并基于单次采集的眼图的渲染方法
公开(公告)号：US06836738B2
公开(公告)日：2004-12-28
申请号：US10389545
申请日：2003-03-14
申请人： Kalev Sepp , John C. Calvin
发明人： Kalev Sepp , John C. Calvin
IPC分类号： G01R2902
CPC分类号： G01R13/029
摘要： A first method for rendering an eye diagram synchronized to a recovered clock and based on a single shot acquisition of a digital storage oscilloscope, acquires a waveform and measures the timing of its edges. It then estimates the symbol rate of the waveform and derives clock signals in accordance with the edge timing and the estimated symbol rate. The waveform data is then sliced into frames with respect to the derived clock signals, and the frames are partially overlapped and aligned to form an eye diagram. In a second embodiment of the invention, the frames are aligned, without being overlapped, to form an eye diagram.
摘要翻译：用于渲染与恢复的时钟同步并基于数字存储示波器的单次采集的眼图的第一种方法，获取波形并测量其边缘的定时。然后，它估计波形的符号率并根据边沿定时和估计的符号率导出时钟信号。然后将波形数据相对于导出的时钟信号切片成帧，并且将帧部分地重叠并对准以形成眼图。在本发明的第二实施例中，框架被对准而不重叠以形成眼图。

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