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1. 发明公开

CN108806742A 随机存取存储器并且具有与其相关的电路、方法以及系统有权
公开(公告)号：CN108806742A
公开(公告)日：2018-11-13
申请号：CN201710749246.2
申请日：2017-08-28
申请人：汤朝景
发明人：汤朝景
IPC分类号： G11C11/417 , G11C11/419
CPC分类号： G11C11/419 , G11C5/147 , G11C7/12 , G11C11/405 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/4085 , G11C11/4087 , G11C11/409 , G11C11/4094 , G11C11/412 , G11C11/418 , G11C2211/4066 , G11C11/417
摘要：最早使用互补式金属氧化物半导体(CMOS)制程技术来实现静态随机存取存储器(SRAM)的晶体管数量是6颗。然后减少晶体管数量则能提高集积密度，然而此举将会降低存储器的稳定性，也有可能提高存取电路的复杂度，因此而增加功率消耗。为了提高SRAM的集积密度，并且根据减少晶体管数量之后所形成的电器特性而设计具有低功率消耗的存储器以及其所对应的电路，然后实现一个存取系统。如果其它各种存储器的电器特性近似于SRAM，像是动态随机存取存储器(DRAM)，那么它们也能使用SRAM所对应的存取电路。

2. 发明申请

US20190139597A1 PSEUDO STATIC RANDOM ACCESS MEMORY AND REFRESH METHOD THEREOF 审中-公开
公开(公告)号：US20190139597A1
公开(公告)日：2019-05-09
申请号：US16121642
申请日：2018-09-05
申请人： Winbond Electronics Corp.
发明人： Yuji Nakaoka
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/408
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/4076 , G11C11/4085 , G11C2211/4066
摘要： A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

3. 发明专利

KR102225114B1 KR102225114B1 - Pseudo static random access memory and method for writing data thereof 有权
公开(公告)号：KR102225114B1
公开(公告)日：2021-03-09
申请号：KR1020190072115A
申请日：2019-06-18
申请人： 윈본드 일렉트로닉스 코포레이션
发明人： 유지 나카오카
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/4091
CPC分类号： G11C11/40615 , G11C11/4076 , G11C11/4091 , G11C2211/4066
摘要： 내부 클록 신호를 조정해, 리프레쉬 동작 및 기입 동작의 경합의 발생을 회피할 수 있는, 의사 SRAM 및 그 데이터 기입 방법을 제공한다. 데이터 기입 방법은, 기본 주기를 가지는 기본 클록 신호를 제공하는 단계와, 칩 인에이블 신호를 유효로 하여 기입 동작을 실행하고, 칩 인에이블 신호가 유효로 되어 있는 시간 구간에서 기입 데이터를 수신하는 단계와, 기입 커맨드 인에이블 신호에 따라, 기본 주기의 간격으로 복수의 내부 클록 신호를 순차 발생하는 단계와, 리프레쉬 경합 신호를 수신하여, 리프레쉬 경합 신호가 유효로 되어 있는지 여부를 판단하는 단계와, 리프레쉬 경합 신호가 유효로 되어 있을 때, 내부 클록 신호를 지연시키고, 지연한 내부 클록 신호에 근거해 기입 데이터를 선택된 센스 앰프에 기입하는 단계를 포함한다.

4. 发明专利

JP2018190480A ランダム・アクセス・メモリ及び関連する回路、方法及びシステム审中-公开
公开(公告)号：JP2018190480A
公开(公告)日：2018-11-29
申请号：JP2018027461
申请日：2018-02-20
申请人：湯朝景
发明人：湯朝景
IPC分类号： H01L21/8244 , H01L27/11 , G11C11/412 , G11C11/405
CPC分类号： G11C11/419 , G11C5/147 , G11C7/12 , G11C11/405 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/4085 , G11C11/4087 , G11C11/409 , G11C11/4094 , G11C11/412 , G11C11/418 , G11C2211/4066
摘要：【課題】少数のトランジスタを用いてSRAMを実現し、記憶状態の安定性を克服し、且つメモリの電力消費を低減すること。【解決手段】 CMOSプロセス技術を使用して、トランジスタ数が6であるSRAMを実現する。次に、集積密度を高めるためにトランジスタ数を減らすが、SRAMは、メモリの安定性が低下し、アクセス回路の複雑さが増し、こうして消費電力が増大する可能性がある。SRAMの集積密度を高めるために、数が減少したトランジスタの電気的特性に従って、メモリを設計することは、低消費電力とそれに対応する回路を含み、次にアクセス・システムを実現する。他の様々なメモリの電気的特性がSRAM(DRAM)に類似している場合に、SRAMの対応するアクセス回路を使用することもできる。【選択図】図4

5. 发明公开

KR1020050066174A 어드레스 홀드 타임 제어 회로 失效
标题翻译：地址保持时间控制电路
公开(公告)号：KR1020050066174A
公开(公告)日：2005-06-30
申请号：KR1020030097425
申请日：2003-12-26
申请人： 에스케이하이닉스 주식회사
发明人： 이경하 , 김창일
IPC分类号： G11C11/4193
CPC分类号： G11C11/408 , G11C8/18 , G11C11/4076 , G11C2211/4066
摘要： 본 발명은 어드레스 홀드 타임 제어 회로에 관한 것으로써, 특히, 슈도우(Pseudo) SRAM(Static Random Access Memory)에서 어드레스 홀드 타임을 정확히 제어할 수 있도록 하는 기술을 개시한다. 이를 위해, 본 발명은 별도의 지연회로를 사용하지 않고, 어드레스 유효 신호와 어드레스 천이 검출 신호를 이용하여 로직적으로 어드레스 홀드 타임을 제어함으로써 디바이스의 리드/라이트 속도 향상과 더불어 레이아웃 면적을 줄일 수 있도록 한다.

6. 发明公开

KR1020030033511A 스토리지 커패시터를 포함하는 셀을 갖는 에스램의리프레쉬장치 및 그 방법 有权
标题翻译：具有包含存储电容器的存储器的复位装置和刷新方法
公开(公告)号：KR1020030033511A
公开(公告)日：2003-05-01
申请号：KR1020010065516
申请日：2001-10-23
申请人： 주식회사 코아매직
发明人： 김태훈
IPC分类号： G11C11/00
CPC分类号： G11C11/40615 , G11C11/4082 , G11C11/4087 , G11C2211/4066
摘要： PURPOSE: A refresh apparatus and a refresh method of an SRAM having a cell including a storage capacitor are provided to perform a refresh operation within the SRAM by improving a structure of a circuit for performing the refresh operation. CONSTITUTION: An internal clock generation portion(100) generates two internal clocks. A refresh timer(300) is used for outputting a signal for indicating a refresh time. A refresh signal generation portion(200) generates a refresh signal according to an internal clock signal and an output signal of the refresh timer(300). A refresh end signal generation portion(400) generates a refresh end signal in response to a row activation signal and the refresh signal. A refresh counter(500) generates an internal address signal. An address buffer(600) is synchronized with a clock edge of the internal clock signal in order to buffer selectively an external address or an internal address of a refresh counter(500). An address transition detection portion(700) detects the address transition from the outputs of the address buffer(600). A detection and sum portion(800) sums up the outputs of each detection portion. A column pass control portion(900) control the activation of a column path.
摘要翻译：目的：提供具有包括存储电容器的单元的SRAM的刷新装置和刷新方法，以通过改进用于执行刷新操作的电路的结构来在SRAM内执行刷新操作。构成：内部时钟产生部分（100）产生两个内部时钟。刷新定时器（300）用于输出用于指示刷新时间的信号。刷新信号生成部（200）根据内部时钟信号和刷新定时器（300）的输出信号生成刷新信号。刷新结束信号生成部分（400）响应于行激活信号和刷新信号产生刷新结束信号。刷新计数器（500）产生内部地址信号。地址缓冲器（600）与内部时钟信号的时钟边沿同步，以便选择性地缓冲刷新计数器（500）的外部地址或内部地址。地址转换检测部分（700）从地址缓冲器（600）的输出检测地址转换。检测和和部分（800）对每个检测部分的输出求和。列通过控制部分（900）控制列路径的激活。

7. 发明公开

KR1020020001975A 어드레스 스큐 프리회로를 가지는 반도체 메모리 장치 失效
标题翻译：具有地址空闲电路的半导体存储器件
公开(公告)号：KR1020020001975A
公开(公告)日：2002-01-09
申请号：KR1020000036332
申请日：2000-06-29
申请人： 삼성전자주식회사
发明人： 박종열 , 김창래 , 정민철 , 한상집
IPC分类号： G11C11/407
CPC分类号： G11C11/40615 , G11C11/4076 , G11C11/408 , G11C2211/4066
摘要： PURPOSE: A semiconductor memory device having an address skew free circuit is provided, which can prevent cell data loss by preventing a plurality of memory cells from being selected as an address skew permission range increases. CONSTITUTION: A memory cell array(9) has a plurality of memory cells connected to a plurality of word lines(WL) and a plurality of bit lines(BL), and one memory cell comprises one transistor and one capacitor. A row decoder(8) selects one of the word lines by decoding a row address signal, and a column decoder(11) selects one of the bit lines through a column gate(12) by decoding a column address signal. A write or a read operation mode is determined by a logic state of a write enable signal(WEB) applied to an I/O gate(13). An address transition sensing circuit(2) generates an ATD pulse by sensing the change of an address being output from an address buffer(1). A pulse extension circuit(3) generates a pulse extended signal ATDD by extending the ATD pulse. An ending edge pulse circuit(4) generates a normal operation enable pulse(NRE) by detecting an ending edge of the extended pulse signal ATDD. A pulse extension and OR gate circuit(5) further extends the extended pulse signal ATDD and generates an NERFH signal by OR-gating.
摘要翻译：目的：提供一种具有地址偏斜自由电路的半导体存储器件，通过防止多个存储单元因地址偏斜允许范围的增加而被选择，从而防止单元数据丢失。构成：存储单元阵列（9）具有连接到多个字线（WL）和多个位线（BL）的多个存储单元，一个存储单元包括一个晶体管和一个电容器。行解码器（8）通过解码行地址信号来选择字线之一，并且列解码器（11）通过对列地址信号进行解码来通过列门选择一个位线。写入或读取操作模式由施加到I / O门（13）的写使能信号（WEB）的逻辑状态确定。地址转换检测电路（2）通过感测从地址缓冲器（1）输出的地址的变化来产生ATD脉冲。脉冲延长电路（3）通过扩展ATD脉冲来产生脉冲扩展信号ATDD。结束边缘脉冲电路（4）通过检测扩展脉冲信号ATDD的结束边沿产生正常工作使能脉冲（NRE）。脉冲扩展和或门电路（5）进一步扩展扩展脉冲信号ATDD，并通过OR门控产生NERFH信号。

8. 发明公开

KR1020040083809A 슈도우 에스램의 구동회로. 无效
标题翻译： PSEUDO SRAM的驱动电路，其中无法提供足够的电压
公开(公告)号：KR1020040083809A
公开(公告)日：2004-10-06
申请号：KR1020030018465
申请日：2003-03-25
申请人： 에스케이하이닉스 주식회사
发明人： 장경식
IPC分类号： G11C11/4193
CPC分类号： G11C11/4074 , G11C11/4091 , G11C2211/4066
摘要： PURPOSE: A driver circuit of a pseudo SRAM is provided to maintain data by supplying an insufficient voltage sufficiently when having a core voltage lower than a driving voltage. CONSTITUTION: A comparator(300) controls a switching unit(310) by outputting a high signal and a low signal selectively by comparing an external voltage with a core voltage. The switching unit outputs a boosting voltage and the core voltage by opening/closing the switch according to a control signal being output from the comparator. And a driver unit(320) is connected to the switching unit and is driven according to the first driving voltage and the second driving voltage.
摘要翻译：目的：提供伪SRAM的驱动电路，以在芯电压低于驱动电压时充分提供足够的电压来维持数据。构成：比较器（300）通过将外部电压与核心电压进行比较来选择性地输出高信号和低信号来控制开关单元（310）。开关单元根据从比较器输出的控制信号，通过开关来输出升压电压和内核电压。并且驱动器单元（320）连接到开关单元，并且根据第一驱动电压和第二驱动电压被驱动。

9. 发明公开

KR1020030002643A 칼럼라인 선택을 위한 방법 및 회로와 이를 이용하는반도체 메모리장치 失效
标题翻译：用于选择列线及其电路的方法以及使用其的半导体存储器件
公开(公告)号：KR1020030002643A
公开(公告)日：2003-01-09
申请号：KR1020010038323
申请日：2001-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 이중섭
IPC分类号： G11C11/4094
CPC分类号： G11C11/4087 , G11C11/4096 , G11C2211/4066
摘要： PURPOSE: A method for a selecting column line and a circuit thereof, and a semiconductor memory device using the same is provided, which is adopted to a pseudo SRAM and realizes an operation like a SRAM using a DRAM cell and thus improving larger integration than the prior the SRAM. CONSTITUTION: According to the method for selecting a column line in a semiconductor memory device, a Y decoder(111) is enabled after a row operation enable signal(rowact) is enabled. And the above enabled Y decoder is disabled in a read mode after the first time, and is disabled after a fixed time from the time when a precharge enable signal(precharge) is enabled in a write mode. The Y decoder is enabled after a global data bus precharge mode is disabled, and is disabled before the global data bus precharge mode is enabled.
摘要翻译：目的：提供一种用于选择列线及其电路的方法，以及使用该方法的半导体存储器件，其用于伪SRAM，并且使用DRAM单元实现像SRAM这样的操作，从而提高比之前的SRAM。构成：根据半导体存储装置中的列线选择方法，在使能了行操作使能信号（rowact）之后，Y解码器（111）被使能。并且上述使能的Y解码器在第一次之后在读取模式下被禁用，并且在从写入模式中启用预充电使能信号（预充电）的时间起的固定时间之后被禁用。在全局数据总线预充电模式被禁止之后，Y解码器被使能，并且在全局数据总线预充电模式被使能之前被禁止。

10. 发明公开

KR1020030033508A 스토리지 커패시터를 포함하는 셀을 가지는 에스램 및 그라이트데이타 입력방법 有权
标题翻译：具有包含存储电容器的SRAM的SRAM及其写入数据的方法
公开(公告)号：KR1020030033508A
公开(公告)日：2003-05-01
申请号：KR1020010065512
申请日：2001-10-23
申请人： 주식회사 코아매직
发明人： 김태훈
IPC分类号： G11C11/00
CPC分类号： G11C11/40615 , G11C11/4082 , G11C11/4087 , G11C11/4093 , G11C11/4096 , G11C2211/4066
摘要： PURPOSE: An SRAM having a cell including a storage capacitor and a method for inputting write data thereof are provided to perform stably a write operation and a refresh operation by improving a structure of a circuit for performing the refresh operation and the write operation. CONSTITUTION: A refresh circuit(100) is used for driving a refresh operation according to a driving operation of a refresh timer. A write enable buffer(113) is used for storing a write enable signal. A delay signal driving portion(110) receives a refresh signal of the refresh circuit(100) and an output signal of the write enable buffer(113) and drives a delay signal. A write latch control portion(111) outputs a write latch control signal in response to a delayed clock of the write enable buffer(113). An address buffer(106) is synchronized with a clock edge of an internal clock signal in order to buffer selectively an external address or an internal address of a refresh counter(105).
摘要翻译：目的：提供具有包括存储电容器的单元的SRAM以及用于输入其写入数据的方法，以通过改进用于执行刷新操作和写入操作的电路的结构来稳定执行写入操作和刷新操作。构成：刷新电路（100）用于根据刷新定时器的驱动操作来驱动刷新操作。写使能缓冲器（113）用于存储写使能信号。延迟信号驱动部分（110）接收刷新电路（100）的刷新信号和写使能缓冲器（113）的输出信号并驱动延迟信号。写锁存器控制部分（111）响应写使能缓冲器（113）的延迟时钟输出写锁存控制信号。地址缓冲器（106）与内部时钟信号的时钟边沿同步，以便选择性地缓冲刷新计数器（105）的外部地址或内部地址。

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