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1. 发明授权

US4696004A Logic analyzer 失效
标题翻译：逻辑分析仪
公开(公告)号：US4696004A
公开(公告)日：1987-09-22
申请号：US737466
申请日：1985-05-24
申请人： Takayuki Nakajima , Tetsuo Aoki , Katsumi Kobayashi , Noboru Akiyama
发明人： Takayuki Nakajima , Tetsuo Aoki , Katsumi Kobayashi , Noboru Akiyama
IPC分类号： G01R31/3177 , G06F11/25 , G06F11/00
CPC分类号： G06F11/25 , G01R31/3177
摘要： Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.
摘要翻译：将从被测电路同时获得的多个通道的逻辑输出数据依次输入到存储器中，并且在输入预定量的这样的数据之后，将它们与相应的预期值进行比较。输入数据被分成块，每个块包括多个数据。每个块的比较结果中是否存在不匹配由相应的块元素指示，并且这些块元素以预定的布置显示。还可以提供包括与存在不匹配的比较结果相对应的输入定时的常规列表显示。

2. 发明授权

US4680540A Device for measuring average frequencies 失效
标题翻译：用于测量平均频率的设备
公开(公告)号：US4680540A
公开(公告)日：1987-07-14
申请号：US629791
申请日：1984-07-11
申请人： Shoji Niki , Toshiro Takahashi , Yohei Hirakoso
发明人： Shoji Niki , Toshiro Takahashi , Yohei Hirakoso
IPC分类号： G01R23/02 , G01R23/00 , G01R23/10
CPC分类号： G01R23/00
摘要： A synchronizing gate signal is generated in synchronism with an input signal or a clock signal, and first and second gates are opened by the synchronizing gate signal. The input signal having passed through the first gate is counted by a first counter circuit, and the clock signal having passed through the second gate is frequency-divided by a divide-by-10.sup.n frequency divider. An output from the frequency divider is counted by a second counter means. The synchronizing gate signal is generated under the control of a control circuit, and is prevented from being generated when the output from the frequency divider is applied to the control circuit. The n in the frequency-division ratio 1/10.sup.n of the frequency divider and a maximum count P of a third counter circuit are determined from a count of the third counter circuit, a preset measurement accuracy, and a period of the clock signal at the time one output is produced from the frequency divider, the n being set in the frequency divider. The control circuit is caused to generate the synchronizing gate signal. When the output from the frequency divider is obtained, the count is picked up from the first counter circuit and the synchronizing gate signal is generated again in a repetitive process. Each time the output from the frequency divider is obtained, an average frequency is calculated from the counts of the first counter circuit and the second counter circuit. Until the count of the second counter circuit reaches P, a display indicates that a displayed average frequency has the preset measurement accuracy.
摘要翻译：同步门信号与输入信号或时钟信号同步产生，第一和第二门由同步门信号打开。通过第一栅极的输入信号由第一计数器电路计数，并且通过第二栅极的时钟信号被除以10n分频器分频。来自分频器的输出由第二计数器计数。在控制电路的控制下产生同步门信号，并且当分频器的输出被施加到控制电路时，防止产生同步门信号。分频器的分频比1 / 10n中的n和第三计数器电路的最大计数P由第三计数器电路的计数，预设的测量精度和时钟信号的周期确定从分频器产生时间一个输出，n分频器中设置n个。使控制电路产生同步门信号。当获得来自分频器的输出时，从第一计数器电路拾取计数，并且在重复处理中再次产生同步门信号。每次获得分频器的输出时，根据第一计数器电路和第二计数器电路的计数来计算平均频率。在第二计数器电路的计数达到P之前，显示器显示所显示的平均频率具有预设的测量精度。

3. 发明授权

US4670879A Pattern generator 失效
标题翻译：模式生成器
公开(公告)号：US4670879A
公开(公告)日：1987-06-02
申请号：US702256
申请日：1985-02-15
申请人： Noboru Okino
发明人： Noboru Okino
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319 , G06F11/22
CPC分类号： G01R31/31921 , G01R31/31908
摘要： In a main pattern memory are stored an increment command pattern and an enable control pattern in addition to test patterns. The main pattern memory is read out with an address from an address control circuit. The increment command pattern thus read out of the main pattern memory instructs incrementing of an address pointer, and a partial pattern memory is read out according to the contents of the address pointer. In accordance with the enable control pattern read out of the main pattern memory, a gate circuit is controlled to open, through which the output of the partial pattern memory is passed, and bits of the passed output are each ORed, by an OR circuit, with the corresponding bits of the test pattern read out of the main pattern memory, providing the ORed output as a test pattern.
摘要翻译：在主图案存储器中除了测试图案之外还存储增量命令模式和使能控制模式。使用地址控制电路的地址读出主模式存储器。因此，从主模式存储器读出的增量命令模式指示地址指针的递增，并且根据地址指针的内容读出部分模式存储器。根据从主模式存储器读出的使能控制模式，通过OR电路控制门电路打开部分模式存储器的输出，并通过输出的位，测试模式的相应位从主模式存储器中读出，提供ORed输出作为测试模式。

4. 发明授权

US4611926A Time interval measuring instrument 失效
标题翻译：时间间隔测量仪
公开(公告)号：US4611926A
公开(公告)日：1986-09-16
申请号：US656853
申请日：1984-10-02
申请人： Mishio Hayashi
发明人： Mishio Hayashi
IPC分类号： G01R23/02 , G01R29/02 , G04F10/04 , G04F8/00
CPC分类号： G01R23/02 , G04F10/04
摘要： An input time signal and clock pulses are provided to a gate, from which the clock pulses are output for a period of time corresponding to the duration of the input time signal, and the clock pulses are applied to a time counter. The time counter is preset, for each measurement, by to a time corresponding to minimum and maximum values of a time interval to be measured and yields a validity signal for a period of time therebetween. The minimum and maximum values of the time interval to be are referenced from the start of the supply of the clock pulses. It is decided and only for whether the validity signal exists at the end of the input time signal, an input time signal that ends during the duration of the validity signal, is its measured duration utilized as valid data.
摘要翻译：将输入时间信号和时钟脉冲提供给门，时钟脉冲从该时钟脉冲输出与输入时间信号的持续时间相对应的时间段，并且时钟脉冲被施加到时间计数器。对于每个测量，时间计数器被预设为与要测量的时间间隔的最小值和最大值相对应的时间，并且在它们之间产生一段时间的有效信号。时钟间隔的最小值和最大值是从提供时钟脉冲的开始所参考的。只决定输入时间信号结束时是否存在有效信号，在有效信号的持续时间内结束的输入时间信号是作为有效数据使用的测量持续时间。

5. 发明授权

US4600994A Phase difference measuring apparatus 失效
标题翻译：相位差测量装置
公开(公告)号：US4600994A
公开(公告)日：1986-07-15
申请号：US538986
申请日：1983-10-04
申请人： Mishio Hayashi
发明人： Mishio Hayashi
IPC分类号： G01R25/00
CPC分类号： G01R25/00
摘要： First and second input signals are waveform-shaped into rectangular wave signals and, in a period measuring mode, one of the rectangular wave signal is input into a time interval measuring circuit and clock pulses are counted during the period of the rectangular wave signal. In a time interval measuring mode, the clock pulses are counted by the time interval measuring circuit over the time interval between one edge of the one rectangular wave signal and the corresponding edge of the other rectangular wave signal, and the phase difference between the first and second input terminals is calculated from the count values.
摘要翻译：第一和第二输入信号是波形形成矩形波信号，并且在周期测量模式中，将矩形波信号中的一个输入到时间间隔测量电路中，并且在矩形波信号的周期期间对时钟脉冲进行计数。在时间间隔测量模式中，时钟脉冲在一个矩形波信号的一个边沿与另一个矩形波信号的相应边缘之间的时间间隔上由时间间隔测量电路进行计数，并且第一和第从计数值计算第二输入端子。

6. 发明授权

US4369432A Auto-calibrated D-A converter 失效
标题翻译：自动校准D-A转换器
公开(公告)号：US4369432A
公开(公告)日：1983-01-18
申请号：US119843
申请日：1980-02-08
申请人： Tsukasa Mikami
发明人： Tsukasa Mikami
IPC分类号： H03M1/00 , H03K13/03
CPC分类号： H03M1/10 , H03M1/82
摘要： A plurality of code signal generators are provided, respectively corresponding to bits of a digital signal to be converted. Each of the code signal generators generates a pulse signal having a duty ratio corresponding to the weight of the corresponding bit of the digital signal. The pulse signal is smoothed to provide a DC output corresponding to the weight of the bit. The outputs from the code signal generators corresponding to the respective bits of the input digital signal are summed by a summing circuit to obtain an analog converted output.
摘要翻译：提供分别对应于要转换的数字信号的位的多个码信号发生器。每个代码信号发生器产生具有对应于数字信号的对应位的权重的占空比的脉冲信号。脉冲信号被平滑以提供对应于该比特的权重的DC输出。来自与输入数字信号的各个比特相对应的代码信号发生器的输出由求和电路相加以获得模拟转换输出。

7. 发明授权

US4112358A Digital frequency measuring device 失效
标题翻译：数字频率测量装置
公开(公告)号：US4112358A
公开(公告)日：1978-09-05
申请号：US785909
申请日：1977-04-08
申请人： Hitoshi Ashida
发明人： Hitoshi Ashida
IPC分类号： G01R23/10 , G04F10/00 , G04F10/10 , G01R23/02
CPC分类号： G04F10/10 , G01R23/10 , G04F10/00
摘要： A digital frequency measuring device in which pulses of an input signal are counted for a certain period of time under the control of a gate signal and the count value is displayed in a digital form. A fraction detector circuit is provided for measuring the time interval or difference .DELTA.T.sub.1 between the leading edge of the gate signal and an input pulse arriving after it, the time interval or difference .DELTA.T.sub.2 between the trailing edge of the gate signal and an input pulse arriving after it and the unit period T of the input pulse signal, and performing an operation corresponding to (.DELTA.T.sub.1 - .DELTA.T.sub.2 /T. The result of operation is converted into the corresponding digital value, which is displayed as a fraction value of the abovesaid count value.
摘要翻译：一种数字频率测量装置，其中在门控信号的控制下输入信号的脉冲在一段时间内被计数，并且计数值以数字形式显示。提供分数检测器电路，用于测量栅极信号的前沿和到达其之后的输入脉冲之间的时间间隔或差值DELTA T1，栅极信号的后沿与输入脉冲之间的时间间隔或差值DELTA T2 输入脉冲信号的单位周期T，并执行与（DELTA T1-DELTA T2 / T）相对应的操作，将运算结果转换成相应的数字值，显示为相应的数字值上述计数值。

8. 发明授权

US4835535A Digital-to-analog converting apparatus equipped with calibrating function 失效
标题翻译：具有校准功能的数模转换设备
公开(公告)号：US4835535A
公开(公告)日：1989-05-30
申请号：US22483
申请日：1987-03-06
申请人： Akinori Shibayama , Hironobu Niijima
发明人： Akinori Shibayama , Hironobu Niijima
IPC分类号： H03M1/10 , G05B19/23 , H03M1/00 , H03M1/74
CPC分类号： G05B19/231 , H03M1/1071 , H03M1/745
摘要： In a D/A converting apparatus which provides a converted analog signal at its output terminal by selectively yielding one or more currents from one or more current sources in accordance with an input digital signal, the current sources are selectively actuated to output the currents and an error in the current of each selected current source is obtained from the output derived at the output terminal in response to the outputting of the current. From the current error of each current source is computed a final error corresponding to each input digital signal and corrected data corresponding to the final error is stored in a corrected data memory, which is read out by the input digital signal. The output thus read out is converted into an analog signal, whereby a correct converted output is obtained.
摘要翻译：在D / A转换装置中，通过根据输入数字信号选择性地产生来自一个或多个电流源的一个或多个电流，在其输出端提供转换的模拟信号，电流源被选择性地致动以输出电流和响应于输出电流，从输出端导出的输出获得每个选定电流源的电流的误差。从每个电流源的当前误差计算出与每个输入数字信号相对应的最终误差，并且对应于最终误差的校正数据被存储在由输入数字信号读出的校正数据存储器中。由此读出的输出被转换为模拟信号，由此获得正确的转换输出。

9. 发明授权

US4477770A Noise field intensity measuring apparatus 失效
标题翻译：噪声场强测量仪
公开(公告)号：US4477770A
公开(公告)日：1984-10-16
申请号：US359137
申请日：1982-03-17
申请人： Shigeki Tojo
发明人： Shigeki Tojo
IPC分类号： G01R15/09 , G01R29/08 , G01R27/00
CPC分类号： G01R29/0814
摘要： A noise wave is received by a receiver and the received output is supplied to a first signal path composed of a rectifier and a low-pass filter connected to the output side thereof. The received output is applied to a second signal path comprised of an AC amplifier, or a rectifier for rectifying the amplified output, a low-pass filter for filtering the rectified output, and an attenuator for attenuating the filtered output. The outputs from the first and second signal paths are selectively provided to a time constant circuit by means of a switch in accordance with the received noise level. The input to the time constant circuit is converted into a quasi-peak value detected output, which is logarithmically amplified by a logarithmic amplifier and is then provided to an indicator.
摘要翻译：接收机接收到噪声波，并且将接收的输出提供给由整流器和连接到其输出侧的低通滤波器组成的第一信号路径。接收的输出被施加到由AC放大器或用于整流放大的输出的整流器，用于滤波整流输出的低通滤波器以及衰减滤波后的输出的衰减器构成的第二信号路径。根据接收到的噪声电平，来自第一和第二信号路径的输出被选择性地提供给时间常数电路。时间常数电路的输入被转换为被测对数输出的准峰值，由对数放大器对数放大，然后提供给指示器。

10. 发明授权

US4313200A Logic test system permitting test pattern changes without dummy cycles 失效
标题翻译：逻辑测试系统允许没有虚拟周期的测试模式更改
公开(公告)号：US4313200A
公开(公告)日：1982-01-26
申请号：US69345
申请日：1979-08-24
申请人： Junji Nishiura
发明人： Junji Nishiura
IPC分类号： G01R31/319 , G06F11/22
CPC分类号： G01R31/31921
摘要： A system for testing logical devices, in which a pattern file is used to store numerous test patterns, each of which includes both an input pattern, which is provided as an input to the device under test, and an expected value pattern, which is compared with the actual output of the device under test to ascertain whether malfunction has occurred. By accessing the pattern file at various addresses, different test patterns can selectively be applied to the device in a test. A command file includes instructions for controlling the sequence in which the various test patterns included in the pattern file are accessed, and an operand file includes data which may be required for carrying out the instructions contained in the command file. Index, stack point, and subroutine return registers are also used to execute the instructions which may be contained in the command file. In addition, provision of a mask data address file with associated structures permits similarly controlled selection of which terminals of the logical device under test are to be tested or disregarded. Thus, by executing a sequence of instructions which are stored in the command file, a very large number of possible test sequences can be executed, without ever interrupting the sequence of input patterns which are applied to the device under test.
摘要翻译：一种用于测试逻辑设备的系统，其中使用模式文件来存储大量测试模式，每个测试模式包括作为被测设备的输入提供的输入模式和被比较的期望值模式与被测设备的实际输出相关，以确定是否发生故障。通过访问各种地址的模式文件，可以在测试中选择性地将不同的测试模式应用于设备。命令文件包括用于控制其中访问包括在模式文件中的各种测试模式的顺序的指令，并且操作数文件包括用于执行包含在命令文件中的指令所需的数据。索引，堆栈点和子程序返回寄存器也用于执行命令文件中可能包含的指令。此外，提供具有关联结构的掩码数据地址文件允许对被测试的逻辑设备的哪些终端进行类似的控制选择来进行测试或忽略。因此，通过执行存储在命令文件中的指令序列，可以执行非常大量的可能的测试序列，而不会中断施加到被测器件的输入模式序列。

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