专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP6932733B2 無線ヘッドセット及び無線ヘッドセットと充電ボックスのアセンブリ有权
公开(公告)号：JP6932733B2
公开(公告)日：2021-09-08
申请号：JP2019033760
申请日：2019-02-27
申请人：瑞▲いー▼半導體股▲ふん▼有限公司 , Realtek Semiconductor Corporation
发明人：沈志祥
IPC分类号： H04R3/00 , H04R1/10

2. 发明公开

US20230266926A1 Memory sharing electronic circuit system and external device capable of storing data in host device 审中-公开
公开(公告)号：US20230266926A1
公开(公告)日：2023-08-24
申请号：US18098723
申请日：2023-01-19
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： YI-CHEN LEE
IPC分类号： G06F3/06
CPC分类号： G06F3/067 , G06F3/0607 , G06F3/0652
摘要： A memory sharing electronic circuit system includes an external device, a transmission interface, and a host device, and allows the external device to store data in the host device. The external device performs a storage operation after receiving input data, wherein the storage operation includes: storing the input data in a device memory of the external device under a first condition; and encapsulating the input data into a data packet with a storage request under a second condition, and transmitting the data packet to the host device via the transmission interface. The host device performs a packet storage operation after receiving the data packet, wherein the packet storage operation includes: parsing the data packet with an Ethernet engine of the host device and thereby allowing the Ethernet engine to store the input data in a host memory of the host device according to the storage request of the data packet.

3. 发明授权

US11736070B2 Amplifier circuit 有权
公开(公告)号：US11736070B2
公开(公告)日：2023-08-22
申请号：US17406248
申请日：2021-08-19
申请人： Realtek Semiconductor Corporation
发明人： Chih-Chan Tu , Chih-Lung Chen , Ka-Un Chan
IPC分类号： H03F3/45 , H03F1/38 , H03F1/34
CPC分类号： H03F1/38 , H03F1/34 , H03F3/45 , H03F2200/153 , H03F2200/408 , H03F2203/45526
摘要： An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

4. 发明公开

US20230260554A1 CONTROLLER, MEMORY DEVICE AND CONTROL METHOD 审中-公开
公开(公告)号：US20230260554A1
公开(公告)日：2023-08-17
申请号：US18147007
申请日：2022-12-28
申请人： Realtek Semiconductor Corporation
发明人： Jing LI , Yongxiang SUN , Wen-Bin WU
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C5/147 , G11C11/4074
摘要： A controller located in a memory device is disclosed. The controller includes a feedback regulation circuit. The feedback regulation circuit is configured to generate a feedback voltage to a power supply circuit according to a power consumption of the controller, for the power supply circuit to adjust an input voltage input to the memory device according to the feedback voltage. When the power consumption of the controller is lower, the feedback voltage is higher, so that the input voltage is lower, and when the power consumption of the controller is higher, the feedback voltage is lower, so that the input voltage is higher.

5. 发明公开

US20230254107A1 Signal communication apparatus and method having re-sampling mechanism 审中-公开
公开(公告)号：US20230254107A1
公开(公告)日：2023-08-10
申请号：US18096186
申请日：2023-01-12
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHIH-HSIU ZENG , CHANG-MING LEE
IPC分类号： H04L7/00 , H04B1/10
CPC分类号： H04L7/0054 , H04B1/1027
摘要： The present invention discloses a signal communication method having re-sampling mechanism that includes steps outlined below. Sampled data of a data signal is obtained. A time difference between an actual sampling time point and an ideal sampling time point is calculated. A closet time point closest to the ideal sampling time point within a sampling time interval is selected. Operation sampled data within a predetermined range around the target sampled data is selected from the sampled data. A group of response terms are retrieved from a pre-stored lookup table according to the closest time point to substitute the response terms and the time difference into a parameter calculation equation to generate a group of re-sampling response parameters. A calculation is performed based on the operation sampled data and the re-sampling response parameters to generate a re-sampled value of the target sampled data.

6. 发明授权

US11722423B2 Data flow classification device 有权
公开(公告)号：US11722423B2
公开(公告)日：2023-08-08
申请号：US17466299
申请日：2021-09-03
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Kuo-Cheng Lu , Min-Chang Wei , Chun-Ming Liu , Kuang-Yu Yen
IPC分类号： H04L47/2441 , H04L47/32 , H04L47/62
CPC分类号： H04L47/2441 , H04L47/32 , H04L47/62
摘要： Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.

7. 发明授权

US11716152B2 Transceiver and transceiver calibration method 有权
公开(公告)号：US11716152B2
公开(公告)日：2023-08-01
申请号：US17728841
申请日：2022-04-25
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Bishen Tseng , Meng Che Li
IPC分类号： H04B17/00 , H04B17/21 , H04B17/11
CPC分类号： H04B17/0085 , H04B17/11 , H04B17/21
摘要： The application discloses a transceiver, including a calibration signal generation unit, a transmission unit, a receiving unit and a control unit. The calibration signal generation unit generates test signal to the transmission unit in a phase calibration mode. The receiving unit generates a digital receiving signal. The control unit calculates a phase difference between the digital receiving signal and a given reference phase and selectively adjust the transmission unit or the receiving unit accordingly. The application discloses a transceiver calibration method as well.

8. 发明授权

US11714555B2 Control module and control method thereof for synchronous dynamic random access memory 有权
公开(公告)号：US11714555B2
公开(公告)日：2023-08-01
申请号：US17376155
申请日：2021-07-15
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Ya-Min Chang
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0673
摘要： The present invention provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

9. 发明公开

US20230230652A1 TESTING SYSTEM AND TESTING METHOD 审中-公开
公开(公告)号：US20230230652A1
公开(公告)日：2023-07-20
申请号：US17814232
申请日：2022-07-22
申请人： Realtek Semiconductor Corporation
发明人： Shih-Chieh LIN , Sheng-Lin LIN , Li-Wei DENG
IPC分类号： G11C29/56 , G11C29/18
CPC分类号： G11C29/56004 , G11C29/56012 , G11C29/18
摘要： A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

10. 发明授权

US11705928B2 Signal predistortion circuit configuration 有权
公开(公告)号：US11705928B2
公开(公告)日：2023-07-18
申请号：US17674865
申请日：2022-02-18
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Wen-Shan Wang , Ming-Chun Hsu
IPC分类号： H04B1/04
CPC分类号： H04B1/0475
摘要： A signal predistortion circuit configuration includes a digital predistortion circuit, a first transceiver, a first analog front-end (AFE) circuit, a second transceiver, and a second AFE circuit. The digital predistortion circuit outputs a first transmission signal according to first predistortion parameters and outputs a second transmission signal according to second predistortion parameters, and the digital predistortion circuit determines whether to adjust the first predistortion parameters according to a first reception signal and determines whether to adjust the second predistortion parameters according to a second reception signal. A transmitting circuit of the first transceiver, the first AFE circuit, and a receiving circuit of the second transceiver jointly generates the first reception signal according to the first transmission signal. A transmitting circuit of the second transceiver, the second AFE circuit, and a receiving circuit of the first transceiver jointly generates the second reception signal according to the second transmission signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式