专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1659499A1 Bus integrating system 审中-公开
标题翻译：公交一体化系统
公开(公告)号：EP1659499A1
公开(公告)日：2006-05-24
申请号：EP04257078.8
申请日：2004-11-16
申请人： RDC Semiconductor Co., Ltd.
发明人： Tsai, Chih-Fu, 6-1F , Hsieh, Chien-Min, 6-1F
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/387
摘要： A bus integrating system (100) is applied to a data processing system. A bus controlling module (110) is coupled to at least one peripheral device for enabling a corresponding device to access data according to a data access request signal sent from the peripheral device. A bus integrating processor (120) includes at least one first bus data access signal pin and at least one second bus data access signal pin (112), so as to allow the bus controlling module to control peripheral devices connected to buses of a first data transmission standard and a second data transmission standard to perform data access with another peripheral device of the same and different data transmission standard via the single bus integrating processor. Thereby, the bus integrating system (100) allows buses with different data transmission standards to transmit data via a single bus and the integrating bus controlling module.
摘要翻译：总线集成系统（100）被应用于数据处理系统。总线控制模块（110）与至少一个外围设备耦合，用于使对应的设备根据从外围设备发送的数据访问请求信号来访问数据。总线集成处理器（120）包括至少一个第一总线数据存取信号引脚和至少一个第二总线数据存取信号引脚（112），以便允许总线控制模块控制连接到第一数据总线的外围设备传输标准和第二数据传输标准，以经由单总线集成处理器与相同且不同数据传输标准的另一外围设备进行数据访问。从而，总线集成系统（100）允许具有不同数据传输标准的总线经由单个总线和集成总线控制模块传输数据。

2. 发明公开

US20240152459A1 METHOD FOR MANAGING MEMORY WRITE REQUEST IN CACHE DEVICE 审中-公开
公开(公告)号：US20240152459A1
公开(公告)日：2024-05-09
申请号：US18113307
申请日：2023-02-23
申请人： RDC Semiconductor Co., Ltd.
发明人： Yao-An TSAI
IPC分类号： G06F12/0831 , G06F12/0897 , G06F13/16
CPC分类号： G06F12/0833 , G06F12/0897 , G06F13/1673
摘要： A method for managing a memory write request in a cache device is provided. The cache device is coupled between a central processing unit and a system memory. The cache memory includes plural levels. An Nth level of the cache device includes an Nth-level command buffer, an Nth-level cache memory and a write allocation buffer, wherein N is an integer larger than 1. The method includes the following steps. Firstly, a request is received from a previous level. If the request is the memory write request, the memory write request is temporarily stored into a free entry of the write allocation buffer. The memory write request contains an address information and a write data. If the request is not the memory write request, the request is temporarily stored into a free entry of the Nth-level command buffer.

3. 发明授权

US09438214B2 DC offset cancellation circuit 有权
标题翻译： DC偏移消除电路
公开(公告)号：US09438214B2
公开(公告)日：2016-09-06
申请号：US14529924
申请日：2014-10-31
申请人： RDC Semiconductor Co., Ltd.
发明人： Ming-Chou Yen
IPC分类号： H03K5/00 , H03K5/003 , H03F1/30 , H03K5/007
CPC分类号： H03K5/003 , H03F1/304 , H03F2200/375 , H03F2203/45212 , H03K5/007
摘要： A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.
摘要翻译：提供DC偏移消除电路。第一直流电流和第一感测电流彼此重叠以产生第一叠加电流。第二直流电流和第二感测电流彼此重叠以产生第二叠加电流。第一叠加电流被转换成第一电压信号。第二叠加电流被转换成第二电压信号。在由差分放大器接收到第一电压信号和第二电压信号之后，产生输出信号。输出信号被处理成DC值。 DC值被转换成直流电流信号。叠加单元根据DC电流信号产生第一DC电流和第二DC电流，使得第一叠加电流和第二叠加电流具有相同的DC偏移。

4. 发明授权

US09342477B2 Multi-core processor, controlling method thereof and computer system with such processor 有权
标题翻译：多核处理器，其控制方法和具有这种处理器的计算机系统
公开(公告)号：US09342477B2
公开(公告)日：2016-05-17
申请号：US13861491
申请日：2013-04-12
申请人： RDC Semiconductor Co., Ltd.
发明人： Chang-Cheng Yap , Ming-Chi Shih
IPC分类号： G06F13/12 , G06F15/00 , G06F15/76 , G06F15/177 , G06F9/50
CPC分类号： G06F15/177 , G06F9/5061
摘要： A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.
摘要翻译：多核处理器包括M个内核。如果多核处理器在非多处理支持操作系统下运行，则只将单个核心配置为中央处理单元，并将N个核心配置为协处理器，其中M和N为正整数，N为较小比M.

5. 发明申请

US20140244975A1 MULTI-CORE PROCESSOR, CONTROLLING METHOD THEREOF AND COMPUTER SYSTEM WITH SUCH PROCESSOR 有权
标题翻译：多核处理器，其控制方法和具有这种处理器的计算机系统
公开(公告)号：US20140244975A1
公开(公告)日：2014-08-28
申请号：US13861491
申请日：2013-04-12
申请人： RDC SEMICONDUCTOR CO., LTD.
发明人： Chang-Cheng Yap , Ming-Chi Shih
IPC分类号： G06F15/76
CPC分类号： G06F15/177 , G06F9/5061
摘要： A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.
摘要翻译：多核处理器包括M个内核。如果多核处理器在非多处理支持操作系统下运行，则只将单个核心配置为中央处理单元，并将N个核心配置为协处理器，其中M和N为正整数，N为较小比M.

6. 发明授权

US08583900B2 Register renaming table recovery method and system for use in a processor 有权
标题翻译：注册重命名表恢复方法和系统，用于处理器
公开(公告)号：US08583900B2
公开(公告)日：2013-11-12
申请号：US12619876
申请日：2009-11-17
申请人： Chien-Nan I , Chun-Wang Wei
发明人： Chien-Nan I , Chun-Wang Wei
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3863
摘要： A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID. Then, a first renamed ID corresponding to a first register is acquired from an unflushed row of the renaming-history table that is immediately adjacent to the flushed ID. If the first renamed ID is occupied, a register renaming table is updated to rename the first register according to the first renamed ID. Whereas, if the first renamed ID is not occupied, the register renaming table is updated to keep the first register unrenamed.
摘要翻译：用于处理器的注册重命名表恢复方法包括以下步骤。首先，根据刷新的ID对重命名历史表进行刷新操作。然后，从与刷新的ID紧邻的重命名历史表的未刷新行获取对应于第一寄存器的第一重命名ID。如果第一个重新命名的ID被占用，则更新注册重命名表，以根据第一个重命名的ID来重命名第一个寄存器。而如果第一个重命名的ID不被占用，则更新注册重命名表以保持第一个寄存器未命名。

7. 发明申请

US20120066476A1 MICRO-OPERATION PROCESSING SYSTEM AND DATA WRITING METHOD THEREOF 审中-公开
标题翻译：微操作处理系统及其数据写入方法
公开(公告)号：US20120066476A1
公开(公告)日：2012-03-15
申请号：US13177801
申请日：2011-07-07
申请人： Cheng Tang CHENG
发明人： Cheng Tang CHENG
IPC分类号： G06F15/76 , G06F9/22
CPC分类号： G06F9/22 , G06F9/38 , G06F9/3824 , G06F9/3836
摘要： A data writing method and a micro-operation processing system are provided. The micro-operation processing system is adapted to access a plurality of registers and each of the registers defines at least one logic storing area. The data writing method comprises the following steps: executing a first micro-operation; selecting a target area of the first micro-operation, which has been updated by the second micro-operation before, as one of the logic storing areas; assigning each of the first micro-operation and the second micro-operation a respective identification number; determining that a execution order of the first micro-operation is later than a execution order of the second micro-operation according to the identification numbers of the first micro-operation and the second micro-operation; and recording that the target area has been updated by the first micro-operation.
摘要翻译：提供数据写入方法和微操作处理系统。微操作处理系统适于访问多个寄存器，并且每个寄存器定义至少一个逻辑存储区域。数据写入方法包括以下步骤：执行第一微操作; 通过第二微操作将已经更新的第一微操作的目标区域选择为逻辑存储区域之一; 将所述第一微操作和所述第二微操作中的每一个分配给相应的识别号码; 根据第一微操作和第二微操作的识别号确定第一微操作的执行顺序晚于第二微操作的执行次序; 并且通过第一微操作来记录目标区域已被更新。

8. 发明申请

US20110191513A1 INTERRUPT CONTROL METHOD AND SYSTEM 审中-公开
标题翻译：中断控制方法和系统
公开(公告)号：US20110191513A1
公开(公告)日：2011-08-04
申请号：US12900031
申请日：2010-10-07
申请人： Chang-Cheng YAP , Ching-Yun CHENG
发明人： Chang-Cheng YAP , Ching-Yun CHENG
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit.
摘要翻译：中央控制系统包括：中央处理单元（CPU）; 外围设备; 中断控制器和中断预处理电路。外围设备可选地发出中断请求，并且中断控制器响应于中断请求产生并输出第一个中断请求信号。中断预处理电路响应于第一个中断请求信号产生并向中断控制器输出两个第一中断确认信号。中断控制器响应于两个第一个中断确认信号产生并输出一个中断向量，并且中断向量通过中断预处理电路发送到CPU。

9. 发明授权

US07543044B2 Automatic configuration system 有权
标题翻译：自动配置系统
公开(公告)号：US07543044B2
公开(公告)日：2009-06-02
申请号：US11430643
申请日：2006-05-09
申请人： Ming-Chou Yen , Chun-Wang Wei , Kun-Ying Tsai
发明人： Ming-Chou Yen , Chun-Wang Wei , Kun-Ying Tsai
IPC分类号： G06F15/177
CPC分类号： H04L41/0886 , H01R29/00 , H04L41/0806
摘要： An automatic configuration system for automatically configuring a connecting interface of a node device in a network is provided. The connecting interface of the node device includes a first pair of connectors and a second pair of connectors. The automatic configuration system includes a switching unit, a first analog circuit unit, a second analog circuit unit and a detecting unit. The detecting unit is used to detect whether a first computed result or a second computed result outputted from the first analog circuit unit or the second analog circuit unit involves signals transmitted from another node device in the network, and accordingly generate a detected result to allow the switching unit to execute a switching operation and selectively connect the transmitting unit to the first or second pair of connectors, so as to ensure that data can be transmitted or received reliably in the network.
摘要翻译：提供一种用于自动配置网络中节点设备的连接接口的自动配置系统。节点设备的连接接口包括第一对连接器和第二对连接器。自动配置系统包括切换单元，第一模拟电路单元，第二模拟电路单元和检测单元。检测单元用于检测从第一模拟电路单元或第二模拟电路单元输出的第一计算结果或第二计算结果是否涉及从网络中的另一节点设备发送的信号，并且因此产生检测结果以允许切换单元执行切换操作并选择性地将发送单元连接到第一或第二对连接器，以便确保可以在网络中可靠地发送或接收数据。

10. 发明授权

US07489740B2 Receiver with baseline wander compensation 有权
标题翻译：接收器与基线漂移补偿
公开(公告)号：US07489740B2
公开(公告)日：2009-02-10
申请号：US11205627
申请日：2005-08-16
申请人： Ming-Chou Yen , Kun-Ying Tsai , Jui-Tai Ko , Chun-Wang Wei
发明人： Ming-Chou Yen , Kun-Ying Tsai , Jui-Tai Ko , Chun-Wang Wei
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： H04L25/063 , H03G3/3089
摘要： A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.
摘要翻译：具有基线漂移补偿的接收机适用于数字通信系统。接收机包括模数转换器（ADC），限幅器，阈值检测器，增益控制器，基线漂移补偿器，延迟电路，模拟增益级和数字增益级。基线漂移补偿器用于对由切片机处理之前获得的电压和处理后的电压执行操作和滤波处理，以获得用于补偿和控制的基线漂移电压值。阈值检测器和增益控制器动态产生模拟增益和数字增益的控制信号。模拟增益级以模拟增益方式补偿通过传输通道的通信信号的劣化。延迟电路用于补偿由ADC执行的转换的延迟。数字增益级补偿模拟增益不足。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式