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1. 发明公开

KR20120135175A Temperature independent reference circuit 审中-公开
标题翻译：温度独立参考电路
公开(公告)号：KR20120135175A
公开(公告)日：2012-12-12
申请号：KR20120133601
申请日：2012-11-23
申请人： POWER INTEGRATIONS INC
发明人： KUNG DAVID , LUND LEIF
IPC分类号： G05F3/00 , G05F3/22 , G05F3/24 , G05F3/26
CPC分类号： G05F3/30
摘要： PURPOSE: A temperature independent reference circuit is provided to reduce total area by replacing a resistor R4 with a transistor MP5. CONSTITUTION: A base and collector of a first bipolar transistor are connected to a base of a second bipolar transistor. First and second resistors are connected between the emitter of the second bipolar transistor and a ground potential. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3, and TC2, respectively. A current mirror is connected to the first and second bipolar transistors.
摘要翻译：目的：提供一个独立于温度的参考电路，通过用晶体管MP5替换电阻R4来减小总面积。构成：第一双极晶体管的基极和集电极连接到第二双极晶体管的基极。第一和第二电阻器连接在第二双极晶体管的发射极和接地电位之间。第一和第二电阻分别具有第一和第二电阻值R1和R2，以及第三和第二温度系数TC3和TC2。电流镜连接到第一和第二双极晶体管。

2. 发明公开

KR20120095334A Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit 审中-公开
标题翻译：集成晶体管和抗保险丝作为高压集成电路的编程元件
公开(公告)号：KR20120095334A
公开(公告)日：2012-08-28
申请号：KR20120075802
申请日：2012-07-11
申请人： POWER INTEGRATIONS INC
发明人： BANERJEE SUJIT , MANLEY MARTIN H
IPC分类号： H01L23/62 , H01L21/335 , H01L29/778
CPC分类号： H01L29/78 , H01L23/5252 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L29/0634 , H01L29/0692 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: An integrated transistor as a programming device for a high voltage integrated circuit and an anti-fuse are provided to reduce the size of a trimming block of a power IC device. CONSTITUTION: A semiconductor device includes an N type well region(47) in a P type substrate(25). A source region of a MOSFET is laterally separated from a boundary of a well region including a drain of the MOSFET. An insulated gate of the MOSFET is laterally extended from the source region via the boundary of the well region. A polysilicon layer forming a first substrate of a capacitive anti-fuse is insulated from the well region forming a second substrate of the anti-fuse. The anti-fuse is programmed to electrically short the polysilicon layer with the drain of a HVFET.
摘要翻译：目的：提供集成晶体管作为高压集成电路和反熔丝的编程装置，以减小功率IC器件的修整块的尺寸。构成：半导体器件包括P型衬底（25）中的N型阱区（47）。 MOSFET的源极区域与包括MOSFET的漏极的阱区域的边界横向分离。 MOSFET的绝缘栅极通过阱区的边界从源极区域横向延伸。形成电容性反熔丝的第一基板的多晶硅层与形成反熔丝的第二基板的阱区绝缘。反熔丝被编程为用HVFET的漏极使多晶硅层电短路。

3. 发明专利

JP2015179679A コントローラおよび電源审中-公开
公开(公告)号：JP2015179679A
公开(公告)日：2015-10-08
申请号：JP2015104357
申请日：2015-05-22
申请人： POWER INTEGRATIONS INC
发明人： YURY GAKNOKI , MAO MINGMING , PASTORE TIZIANO
IPC分类号： H05B37/02 , H02M3/28
摘要：【課題】電源へのac入力電圧のゼロ交差を判定するための方法および装置を提供する。【解決手段】スイッチモード電源(100)のための例示的なコントローラ(138,938)は、駆動信号生成器(902,904)およびゼロ交差検出器(906)を含む。駆動信号生成器(902,904)は、電源(100)に含まれるスイッチ(S1 114)のスイッチングを制御して電源(100)の出力を調整するように結合されるものである。ゼロ交差検出器(906)は駆動信号生成器(902,904)に結合され、スイッチ(S1 114)を通って流れるスイッチ電流を表わす電流検知信号を受けるように結合される。ゼロ交差検出器(906)は、電流検知信号とゼロ交差電流しきい値を表わす参照信号との比較に応答してゼロ交差信号を生成する。ゼロ交差信号は、電源(100)のacライン入力電圧のゼロ交差条件がいつ存在するかを示す。【選択図】図1

4. 发明专利

JP2014170934A Heterostructure power transistor and heterostructure semiconductor device manufacturing method 有权
标题翻译：异构结构功率晶体管和异质结半导体器件制造方法
公开(公告)号：JP2014170934A
公开(公告)日：2014-09-18
申请号：JP2014036673
申请日：2014-02-27
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： RAMDANI JAMAL , MICHAEL MURPHY , JOHN PAUL EDWARDS
IPC分类号： H01L29/812 , H01L21/318 , H01L21/336 , H01L21/338 , H01L29/778 , H01L29/78
CPC分类号： H01L29/7787 , H01L21/02107 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42364 , H01L29/42376 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462
摘要： PROBLEM TO BE SOLVED: To provide a GaN-based HFET device structure and a manufacturing method of the same.SOLUTION: A heterostructure semiconductor device 100 comprises: a first active layer 102; a second active layer 106 arranged on the first active layer 102; two-dimensional electronic gas layer 104 formed between the first active layer 102 and the second active layer 106; an AlSiN passivation layer 108 arranged on the second active layer 106; first and second ohmic contacts 114, 116 which are electrically connected to the second active layer 106 and separated from each other in a lateral direction; and a gate 112 arranged between the first ohmic contact 114 and the second ohmic contact 116.
摘要翻译：要解决的问题：提供GaN基HFET器件结构及其制造方法。解决方案：异质结构半导体器件100包括：第一有源层102; 布置在第一有源层102上的第二有源层106; 形成在第一有源层102和第二有源层106之间的二维电子气体层104; 布置在第二有源层106上的AlSiN钝化层108; 第一和第二欧姆接触114,116，其电连接到第二有源层106并且在横向上彼此分离; 以及布置在第一欧姆接触114和第二欧姆接触116之间的门112。

5. 发明专利

JP2014100062A Method and apparatus for control circuit responding to impedance coupled to control circuit terminal 审中-公开
标题翻译：用于控制回路的控制电路的方法和装置与阻抗相关联以控制电路终端
公开(公告)号：JP2014100062A
公开(公告)日：2014-05-29
申请号：JP2014036736
申请日：2014-02-27
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： WANG ZHAO-JUN , BAURLE STEFAN , MATTHEWS DAVID MICHAEL HUGH
IPC分类号： H02M3/28
CPC分类号： H02M3/33523 , H02M1/32 , H02M3/33507
摘要： PROBLEM TO BE SOLVED: To provide a power supply controller method and apparatus for measuring impedance.SOLUTION: An apparatus according to an embodiment of the present invention comprises a sense circuit coupled to a sensing terminal. A regulation circuit is coupled to the sensing circuit, and coupled to regulate the sensing terminal to a first voltage level when current flowing through the sensing terminal is smaller than a first threshold current level. The regulation circuit is further coupled to regulate the sensing terminal to a second voltage level when the current flowing through the sensing terminal reaches the first threshold current level. A response circuit is coupled to the sensing circuit and responsive to the current flowing through the sensing terminal when the sensing terminal is regulated at the second voltage level.
摘要翻译：要解决的问题：提供一种用于测量阻抗的电源控制器方法和装置。解决方案：根据本发明的实施例的装置包括耦合到感测端子的感测电路。调节电路耦合到感测电路，并且当流过感测端子的电流小于第一阈值电流电平时，耦合到将感测端子调节到第一电压电平。当流过感测端的电流达到第一阈值电流电平时，调节电路进一步耦合以将感测端调节到第二电压电平。当感测端被调节在第二电压电平时，响应电路耦合到感测电路并且响应于流过感测端的电流。

6. 发明专利

JP2014060918A Power converter and method for regulating output of power converter 审中-公开
标题翻译：用于调节功率转换器输出的功率转换器和方法
公开(公告)号：JP2014060918A
公开(公告)日：2014-04-03
申请号：JP2013244829
申请日：2013-11-27
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： DJENGUERIAN ALEX B , BALAKRISHNAN BALU , BIRCAN ERDEM
IPC分类号： H02M3/28
CPC分类号： H02M3/33515 , H02M3/157
摘要： PROBLEM TO BE SOLVED: To provide a power converter control method and apparatus.SOLUTION: The power converter controller includes: a feedback sampling circuit 170 to be coupled to an output of a power converter 100 to generate feedback sample signals U175 during enabled switching cycles; and a switch conduction control circuit 185 coupled to the feedback sampling circuit 170 which includes a switch conduction enable circuit that is coupled to enable or disable the conduction of a power switch 120 during a switching cycle in response to the feedback sample signals U175, and a switch conduction scheduling circuit that is coupled to determine a varying number of future enabled and disabled switching cycles in response to the feedback sample signals U175 from a present switching cycle and one or more past switching cycles.
摘要翻译：要解决的问题：提供一种功率转换器控制方法和装置。解决方案：功率转换器控制器包括：反馈采样电路170，其被耦合到功率转换器100的输出端，以在可用的开关周期期间产生反馈采样信号U175; 以及耦合到反馈采样电路170的开关导通控制电路185，其包括开关导通使能电路，其被耦合以响应于反馈采样信号U175而在开关周期期间启用或禁用功率开关120的导通，以及开关导通调度电路，其被耦合以响应于来自当前开关周期的反馈采样信号U175和一个或多个过去的开关周期来确定将来启用和禁用的开关周期的变化数量。

7. 发明专利

JP2013118377A Method for manufacturing multilayer structure for power transistor device, method for manufacturing multilayer structure for heterojunction field-effect transistor device, and nitride-based heterojunction field-effect transistor device 审中-公开
标题翻译：用于制造用于功率晶体管器件的多层结构的方法，用于制造用于异质场效应晶体管器件的多层结构的方法和基于氮化物的异质场效应晶体管器件
公开(公告)号：JP2013118377A
公开(公告)日：2013-06-13
申请号：JP2012262399
申请日：2012-11-30
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： RAMDANI JAMAL , LIU LIN LIN , JOHN PAUL EDWARDS
IPC分类号： H01L21/338 , H01L21/318 , H01L21/336 , H01L29/06 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812
CPC分类号： H01L29/66462 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02274 , H01L21/02315 , H01L21/0234 , H01L21/28264 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/402 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/778 , H01L29/7786 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a group III nitride-based compound semiconductor device and a method for manufacturing the same.SOLUTION: The method for manufacturing the multilayer structure for the power transistor device includes the steps of: striking a nitrogen plasma in a reaction chamber to thereby form a nitride layer just above a nitride-based active semiconductor layer; exposing the upper face of the nitride layer on a second source; and striking a nitrogen-oxygen plasma to thereby form an oxynitride layer just above the nitride layer. The nitride layer includes a passivation layer, and the oxynitride layer includes a gate dielectric of the power transistor device.
摘要翻译：解决的问题：提供III族氮化物系化合物半导体器件及其制造方法。解决方案：用于制造功率晶体管器件的多层结构的方法包括以下步骤：在反应室中击打氮等离子体，从而在氮化物基有源半导体层正上方形成氮化物层; 将氮化物层的上表面暴露在第二源上; 并且冲击氮 - 氧等离子体，从而在氮化物层正上方形成氧氮化物层。氮化物层包括钝化层，氮氧化物层包括功率晶体管器件的栅极电介质。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2013070604A Power supply controller 有权
标题翻译：电源控制器
公开(公告)号：JP2013070604A
公开(公告)日：2013-04-18
申请号：JP2012208291
申请日：2012-09-21
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： MING MING MAO
IPC分类号： H02M3/28
CPC分类号： H02M3/33523 , H02M2001/0035 , Y02B70/16
摘要： PROBLEM TO BE SOLVED: To provide a primary side controller to prevent an effective switching frequency within an undesired audible frequency range at low cost while appropriately controlling an output of power supply.SOLUTION: The power supply controller is disclosed. An example power supply controller includes a signal separator circuit coupled to generate a feedback signal in response to a detection signal representative of an output of a power supply. An error signal generator is coupled to generate an error signal in response to the feedback signal and a reference signal. A control circuit is coupled to generate a drive signal in response to the error signal and a current detection signal. The drive signal is coupled to control switching of a switch of the power supply. A multi-cycle modulation circuit is included in the control circuit and is coupled to generate a skip signal in response to a start skip signal, a stop skip signal and a skip mask signal.
摘要翻译：要解决的问题：提供一个初级侧控制器，以便在适当地控制电源的输出的同时以低成本防止在不期望的可听频率范围内的有效开关频率。
解决方案：公开了电源控制器。示例性电源控制器包括耦合以响应于代表电源的输出的检测信号而产生反馈信号的信号分离器电路。耦合误差信号发生器以响应于反馈信号和参考信号产生误差信号。控制电路被耦合以响应于误差信号和电流检测信号而产生驱动信号。驱动信号被耦合以控制电源的开关的切换。多周期调制电路包括在控制电路中，并且被耦合以响应于起始跳过信号，停止跳过信号和跳过屏蔽信号而产生跳跃信号。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2013065898A Apparatus and method for fast recovery rectifier structure 有权
标题翻译：快速恢复整流器结构的装置和方法
公开(公告)号：JP2013065898A
公开(公告)日：2013-04-11
申请号：JP2013000246
申请日：2013-01-04
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： RICHARD FRANCIS , FAN YANG YU , ERIC JOHNSON , HOANG HY
IPC分类号： H01L29/47 , H01L21/337 , H01L21/338 , H01L27/095 , H01L27/098 , H01L29/808 , H01L29/812 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872 , H01L27/0641 , H01L27/0814 , H01L27/0817 , H01L29/0623 , H01L29/7722 , H01L29/8083 , H01L29/861 , H01L29/8725
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method for a fast recovery rectifier structure.SOLUTION: Specifically, the structure includes a substrate (120) of a first dopant. A first epitaxial layer (140) lightly doped with the first dopant is coupled to the substrate. A first metallization layer (190) is coupled to the first epitaxial layer. A plurality of trenches (175) are recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The apparatus also includes a plurality of wells each doped with a second dopant type, where each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers (170) are formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant are formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions (150) are more highly doped with the first dopant than the first epitaxial layer.
摘要翻译：要解决的问题：提供一种用于快速恢复整流器结构的装置和方法。具体地，该结构包括第一掺杂剂的衬底（120）。轻掺杂有第一掺杂剂的第一外延层（140）被耦合到衬底。第一金属化层（190）耦合到第一外延层。多个沟槽（175）凹陷到第一外延层中，每个沟槽耦合到金属化层。该装置还包括多个阱，每个阱均掺杂有第二掺杂剂类型，其中每个阱形成在相应的沟槽下面并与其相邻。多个氧化物层（170）形成在相应沟槽的壁和底部上。掺杂有第一掺杂剂的多个沟道区在两个对应的阱之间的第一外延层内形成。多个通道区域（150）中的每一个与第一外延层相比第一掺杂物更加高掺杂。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2013042183A Non-activated guard ring for semiconductor device 审中-公开
标题翻译：用于半导体器件的非激活保护环
公开(公告)号：JP2013042183A
公开(公告)日：2013-02-28
申请号：JP2012257871
申请日：2012-11-26
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： CERUZZI ALEX D , POPHRISTIC MILAN , SHELTON BRYAN S , LIU LINLIN , MURPHY MICHAEL , ZHU TING GANG
IPC分类号： H01L29/47 , H01L21/329 , H01L21/44 , H01L29/872
CPC分类号： H01L29/32 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/2003 , H01L29/207 , H01L29/452 , H01L29/475 , H01L29/66143 , H01L29/66212 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, and particularly, the semiconductor device which incorporates a metal-semiconductor rectifying junction, such as a Schottky diode.SOLUTION: A guard ring is formed in a semiconductor region that is a part of Schottky junction or a Schottky diode. The guard ring is formed by ion implantation into a semiconductor contact layer, without completely annealing the semiconductor contact layer, for forming a high resistance region. The guard ring can be located at an edge part of the layer or, alternatively at a certain distance away from the edge part of the layer. A Schottky metal contact is formed on the layer, and an edge part of the Schottky contact is disposed on the guard ring.
摘要翻译：要解决的问题：提供一种半导体器件，特别是包括诸如肖特基二极管的金属半导体整流结的半导体器件。解决方案：在作为肖特基结或肖特基二极管的一部分的半导体区域中形成保护环。保护环通过离子注入形成半导体接触层，而不完全退火半导体接触层，以形成高电阻区域。保护环可以位于层的边缘部分，或者可选地在距离层的边缘部分一定距离处。肖特基金属触点形成在该层上，肖特基触点的边缘部分设置在保护环上。版权所有（C）2013，JPO＆INPIT

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