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1. 发明申请

WO2014034691A1 CHIP STACK, SEMICONDUCTOR DEVICES HAVING THE SAME, AND MANUFACTURING METHODS FOR CHIP STACK 审中-公开
标题翻译：芯片堆叠，具有相同功能的半导体器件以及芯片堆栈的制造方法
公开(公告)号：WO2014034691A1
公开(公告)日：2014-03-06
申请号：PCT/JP2013/072926
申请日：2013-08-21
申请人： PS4 LUXCO S.A.R.L. , YOSHIDA, Masanori
发明人： YOSHIDA, Masanori
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/50 , H01L21/56 , H01L21/563 , H01L23/3128 , H01L23/3135 , H01L23/49838 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06555 , H01L2225/06565 , H01L2924/1431 , H01L2924/1434
摘要： A chip stack (11) is configured by stacking at least first, second, and third semiconductor chips (10a, 10b, 10c). The first semiconductor chip (10a) has bump electrodes formed only on one side thereof. The second semiconductor chip (10b) has bump electrodes formed on both sides thereof and they are electrically connected each other. The second semiconductor chip (10b) is stacked on and electrically connected to the first semiconductor chip (10a) through a first solder layer. The third semiconductor chip (10c) has bump electrodes formed on both sides thereof and they are electrically connected each other. Second and third solder layers are formed on the bump electrodes on the both sides of the third semiconductor chip. The third semiconductor chip (10c) is stacked on and electrically connected to the second semiconductor chip (10b) through the third solder layer.
摘要翻译：芯片堆叠（11）通过堆叠至少第一，第二和第三半导体芯片（10a，10b，10c）构成。第一半导体芯片（10a）仅在其一侧形成凸起电极。第二半导体芯片（10b）具有形成在其两侧的凸起电极，并且它们彼此电连接。第二半导体芯片（10b）通过第一焊料层堆叠并电连接到第一半导体芯片（10a）。第三半导体芯片（10c）具有形成在其两侧的凸起电极，并且它们彼此电连接。第二和第三焊料层形成在第三半导体芯片两侧的凸块电极上。第三半导体芯片（10c）通过第三焊料层层叠并与第二半导体芯片10b电连接。

2. 发明申请

WO2014050051A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2014050051A1
公开(公告)日：2014-04-03
申请号：PCT/JP2013/005570
申请日：2013-09-20
申请人： PS4 LUXCO S.A.R.L. , OYU, Kiyonori
发明人： OYU, Kiyonori
IPC分类号： H01L21/8242 , H01L21/76 , H01L27/108
CPC分类号： H01L27/10876 , H01L21/76224
摘要： Disclosed herein is a semiconductor device that includes: a semiconductor substrate; a well of a first conductive type that is formed in the semiconductor substrate; an element isolation region embedded in the semiconductor substrate so as to define an active region of the well; first and second gate electrodes each including a side surface and a bottom surface that are covered with the well such that the first and second gate electrodes are formed to traverse the active region, and a peak depth of the well corresponding to the active region is equal to or shallower than a peak depth of the well corresponding to the element isolation region.
摘要翻译：本文公开了一种半导体器件，其包括：半导体衬底; 在半导体衬底中形成的第一导电类型的阱; 元件隔离区域，嵌入在所述半导体衬底中，以限定所述阱的有源区; 第一和第二栅电极，每个包括被阱覆盖的侧表面和底表面，使得第一和第二栅电极形成为穿过有源区，并且与有源区相对应的阱的峰深度相等比对应于元件隔离区域的阱的峰深度更深或更浅。

3. 发明申请

WO2014034084A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2014034084A1
公开(公告)日：2014-03-06
申请号：PCT/JP2013/005030
申请日：2013-08-26
申请人： PS4 LUXCO S.A.R.L. , KITAGAWA, Katsuhiro , TAKAHASHI, Hiroki , NAKAMURA, Kohei
发明人： KITAGAWA, Katsuhiro , TAKAHASHI, Hiroki , NAKAMURA, Kohei
IPC分类号： H03K5/08 , G11C11/4093 , H03F3/45 , H03K5/24
CPC分类号： H03F1/0205 , G11C7/1084 , G11C11/4093 , H03F3/45076 , H03F2203/45182 , H03K5/2481
摘要： A semiconductor device comprises a first input terminal; a second input terminal; an inverting amplifier circuit that comprises an input node connected to a first input terminal, an inverting input node connected to a second input terminal, and an output node connected to an output terminal, amplifies a difference between a first input signal supplied to the input node and a second input signal supplied to the second input terminal, and that outputs an output signal whose polarity is inverted from that of the first input signal to the output node; and a non-inverting amplifier circuit that comprises an input node connected to a second input terminal, an inverting input node connected to a first input terminal, and an output node connected to an output terminal, amplifies a difference between the first input signal and the second input signal, and that outputs an output signal whose polarity is the same as that of the first input signal to the output node.
摘要翻译：半导体器件包括第一输入端; 第二输入端; 反相放大器电路，包括连接到第一输入端子的输入节点，连接到第二输入端子的反相输入节点和连接到输出端子的输出节点，放大提供给输入节点的第一输入信号以及第二输入信号，其被提供给所述第二输入端，并将其极性与所述第一输入信号的极性反相的输出信号输出到所述输出节点; 以及非反相放大器电路，其包括连接到第二输入端子的输入节点，连接到第一输入端子的反相输入节点和连接到输出端子的输出节点，放大第一输入信号和第二输入信号，并且将与第一输入信号的极性相同的输出信号输出到输出节点。

4. 发明申请

WO2014128246A1 METHOD AND DEVICE FOR STORING AND READING RELIABLE INFORMATION IN A NAND ARRAY 审中-公开
标题翻译：用于在NAND阵列中存储和读取可靠信息的方法和设备
公开(公告)号：WO2014128246A1
公开(公告)日：2014-08-28
申请号：PCT/EP2014/053399
申请日：2014-02-21
申请人： PS4 LUXCO S.A.R.L.
发明人： MARTINOZZI, Giulio , SIVERO, Stefano
IPC分类号： G11C16/34 , G11C16/20 , G11C29/00
CPC分类号： G11C29/04 , G11C16/0408 , G11C16/20 , G11C16/349 , G11C29/76 , G11C2211/5642 , G11C2229/723
摘要： A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets.
摘要翻译：方法（和装置）包括在存储器的页面区域中产生第一数据，第一数据包括第一数量的存储器组，每个存储器组具有第二数量的位，其中第一个数是更多的正数超过一个，第二个数字是三个以上的正数。在产生存储器的页面区域中的第一数据之后，响应于所产生的第一数据产生第二数据，第二数据具有第一位数，第二数据的每个位具有逻辑值即由包括在相应的一个存储器组中的大部分位确定。

5. 发明申请

WO2014050917A1 TEST CARRIER, TESTER, TEST METHOD FOR SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR TESTED SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE MANUFACTURING METHOD 审中-公开
标题翻译：测试载体，测试仪，半导体器件的测试方法，测试半导体器件的制造方法和使用制造方法制造的半导体器件
公开(公告)号：WO2014050917A1
公开(公告)日：2014-04-03
申请号：PCT/JP2013/075962
申请日：2013-09-18
申请人： PS4 LUXCO S.A.R.L. , MAEDA, Naoto , ISHIKAWA, Toru
发明人： MAEDA, Naoto , ISHIKAWA, Toru
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R1/0483 , H01L24/16 , H01L25/0657 , H01L2224/16146 , H01L2224/16238 , H01L2224/17154 , H01L2224/17181 , H01L2225/06513 , H01L2225/06565
摘要： A method of producing a tested semiconductor device includes preparing a semiconductor device. The semiconductor device includes a first chip including via electrodes that pierce a substrate; a second chip associated with the first chip; a power supply terminal that supplies electric power to the first chip or the second chip; and a plurality of signal terminals corresponding to a plurality of signals associated with the first chip or the second chip. The method includes preparing a test unit. The test unit includes a first terminal, a second terminal, and a third terminal corresponding to the power supply terminal of the semiconductor device; a first wiring that connects the first terminal with the second terminal; and a second wiring that connects the first terminal with the third terminal. The method includes bringing the first terminal and the power supply terminal into contact with each other and testing the semiconductor device.
摘要翻译：制造被测半导体器件的方法包括制备半导体器件。半导体器件包括：第一芯片，其包括穿透基板的通孔电极; 与第一芯片相关联的第二芯片; 向第一芯片或第二芯片供电的电源端子; 以及对应于与第一芯片或第二芯片相关联的多个信号的多个信号端子。该方法包括准备一个测试单元。测试单元包括第一端子，第二端子和对应于半导体器件的电源端子的第三端子; 将所述第一端子与所述第二端子连接的第一布线; 以及将第一端子与第三端子连接的第二布线。该方法包括使第一端子和电源端子彼此接触并测试半导体器件。

6. 发明申请

WO2014030760A1 DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：装置及其制造方法
公开(公告)号：WO2014030760A1
公开(公告)日：2014-02-27
申请号：PCT/JP2013/072638
申请日：2013-08-20
申请人： PS4 LUXCO S.A.R.L. , KINDO, Osamu
发明人： KINDO, Osamu
IPC分类号： H01L25/065 , H01L21/56 , H01L23/28 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49838 , B29C45/14311 , B29C45/14655 , B29C45/2669 , B29C45/34 , B29C2045/14327 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/3142 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/48145 , H01L2224/48227 , H01L2224/48228 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06558 , H01L2225/06562 , H01L2924/00014 , H01L2924/10162 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/18301 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2924/00011
摘要： A device includes a substrate having a base member and an insulation film formed on a surface of the base member, a first semiconductor chip mounted over a surface of the substrate on which the insulation film are formed, a second semiconductor chip stacked over the first semiconductor chip so that an overhang portion is formed, and a sealing member formed on the substrate so that the first semiconductor chip and the second semiconductor chip are covered with the sealing member. The insulation film has a first opening portion in a first area of the substrate that overlaps the overhang portion. The base member has an air passage communicating with the first opening portion.
摘要翻译：一种器件包括：具有基底构件和形成在基底构件表面上的绝缘膜的基板，安装在其上形成有绝缘膜的基板的表面上的第一半导体芯片，堆叠在第一半导体上的第二半导体芯片形成突出部，以及形成在基板上的密封部件，使得第一半导体芯片和第二半导体芯片被密封部件覆盖。所述绝缘膜具有与所述突出部重叠的所述基板的第一区域中的第一开口部。基座部件具有与第一开口部连通的空气通路。

7. 发明申请

WO2014050050A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED WORD LINES 审中-公开
标题翻译：具有分层结构化字线的半导体器件
公开(公告)号：WO2014050050A1
公开(公告)日：2014-04-03
申请号：PCT/JP2013/005569
申请日：2013-09-20
申请人： PS4 LUXCO S.A.R.L. , OHATA, Munetoshi , EDO, Sachiko , KOSHITA, Gen
发明人： OHATA, Munetoshi , EDO, Sachiko , KOSHITA, Gen
IPC分类号： G11C11/407 , G11C11/4074
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4087 , G11C11/4097
摘要： Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode.
摘要翻译：这里公开了一种半导体器件，其包括：存储单元阵列，包括排列在子字线和位线的交点处的子字线，位线和存储单元; 多个子字驱动器每个驱动相关联的一个子字线; 并且多个主字驱动器各自向相关联的一个子字驱动器提供具有选择电平电位和未选择电平电位之一的主字信号。当相关联的一个主字信号具有所选电平的电位时，每个子字驱动器将相关联的一个子字线驱动到活动电平，并将相关联的一个子字线驱动到当相关联的一个主字信号具有未选择电平的电位时，不起作用的电平。主字信号的未选择电平可根据操作模式而变化。

8. 发明申请

WO2014045598A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2014045598A1
公开(公告)日：2014-03-27
申请号：PCT/JP2013/005596
申请日：2013-09-20
申请人： PS4 LUXCO S.A.R.L. , KAJIGAYA, Kazuhiko
发明人： KAJIGAYA, Kazuhiko
IPC分类号： G11C11/15 , G11C13/00
CPC分类号： G11C13/004 , G11C5/025 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C13/0069 , G11C2013/0045 , G11C2013/0078 , G11C2213/79
摘要： A semiconductor device comprises memory cell array including first memory cell connected between first terminal and second terminal, written to first resistive state by applying voltage in first direction to first memory cell, and written to second resistive state by applying voltage in second direction different from first direction to first memory cell, first line and second line connected to first terminal and second terminal, respectively, third terminal receiving control signal, and first writing circuit comprising first input terminal connected to third terminal, second input terminal connected to one end of second line, and first output terminal connected to one end of first line, and first writing circuit being configured to control first line based on control signal of first input terminal and signal of second input terminal transmitted via second line.
摘要翻译：半导体器件包括存储单元阵列，其包括连接在第一端子和第二端子之间的第一存储单元，通过向第一存储单元施加第一方向的电压而写入第一电阻状态，并且通过沿与第一存储器单元不同的第二方向施加电压来写入第二电阻状态分别与第一端子和第二端子连接的第一线路和第二线路，第三端子接收控制信号，以及第一写入电路，包括连接到第三端子的第一输入端子，连接到第二线路的一端的第二输入端子，第一输出端子连接到第一线路的一端，第一写入电路被配置为基于第一输入端子的控制信号和经由第二线路发送的第二输入端子的信号来控制第一线路。

9. 发明申请

WO2014030756A1 Semiconductor Device having an amplifying circuit 审中-公开
标题翻译：具有放大电路的半导体器件
公开(公告)号：WO2014030756A1
公开(公告)日：2014-02-27
申请号：PCT/JP2013/072633
申请日：2013-08-19
申请人： PS4 LUXCO S.A.R.L. , ASAKI, Kenji , SHIOKAWA, Miku , ARAI, Tetsuya
发明人： ASAKI, Kenji , SHIOKAWA, Miku , ARAI, Tetsuya
IPC分类号： H03F3/45 , H03K5/08
CPC分类号： H03F1/0211 , H03F3/45076 , H03F3/45183 , H03F2200/231 , H03F2203/45112 , H03F2203/45726 , H03F2203/45728 , H03K5/2481
摘要： A semiconductor device includes a voltage comparing circuit, an amplifying circuit and a control circuit. The voltage comparing circuit includes first and second transistors that are coupled in a differential manner to compare first and second input voltages. The amplifying circuit amplifies an output voltage of the voltage comparing circuit to produce an amplified signal and holds the amplified signal. The control circuit is configured, when activated, to cut off a current path though which a current flows from the amplifying circuit. The current path includes a serial connection of the first and second transistors.
摘要翻译：半导体器件包括电压比较电路，放大电路和控制电路。电压比较电路包括以差分方式耦合以比较第一和第二输入电压的第一和第二晶体管。放大电路放大电压比较电路的输出电压以产生放大的信号并保持放大的信号。控制电路在被激活时被配置为切断电流从放大电路流过的电流路径。电流路径包括第一和第二晶体管的串联连接。

10. 发明申请

WO2014027469A1 SEMICONDUCTOR DEVICE WITH FLOATING BODY STRUCTURE 审中-公开
标题翻译：具有浮动体结构的半导体器件
公开(公告)号：WO2014027469A1
公开(公告)日：2014-02-20
申请号：PCT/JP2013/004898
申请日：2013-08-19
申请人： PS4 LUXCO S.A.R.L. , MOCHIDA, Noriaki , MATSUMOTO, Yasuhiro , NAKAI, Izumi
发明人： MOCHIDA, Noriaki , MATSUMOTO, Yasuhiro , NAKAI, Izumi
IPC分类号： G11C11/4091 , G11C11/4094
CPC分类号： G11C8/08 , G11C7/02 , G11C7/04 , G11C7/222 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/005 , H01L27/092 , H01L27/10897 , H01L29/7841
摘要： A semiconductor device is disclosed, which comprises: a memory cell, first and second bit lines, a switch between the first and second bit lines, a sense amplifier, a sense amplifier driving circuit driving the sense amplifier with first and second voltages, a precharge circuit precharging the first bit line, and a control circuit. The control circuit performs a read operation so that the first and second bit lines are disconnected from each other and the first bit line is precharged to a precharge voltage, during a first period. Thereafter, the control circuit performs a restoring operation in a state where the first and second bit lines are connected to each other and the precharging of the first bit line is cancelled, during a second period after the first period. The sense amplifier is driven with the second voltage for increasing its driving ability during the second period
摘要翻译：公开了一种半导体器件，其包括：存储单元，第一和第二位线，第一和第二位线之间的开关，读出放大器，用第一和第二电压驱动读出放大器的读出放大器驱动电路，预充电电路对第一位线进行预充电，以及控制电路。控制电路执行读取操作，使得第一位线和第二位线在第一周期期间彼此断开并且第一位线被预充电为预充电电压。此后，在第一时段之后的第二时段期间，控制电路在第一和第二位线彼此连接并且第一位线的预充电被取消的状态下执行恢复操作。读出放大器用第二电压驱动，以提高其在第二周期内的驱动能力

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