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1. 发明申请

WO1998036417A1 CLOCK DOUBLER AND MINIMUM DUTY CYCLE GENERATOR FOR SDRAMS 审中-公开
标题翻译：时钟双重器和最小占空比发电机
公开(公告)号：WO1998036417A1
公开(公告)日：1998-08-20
申请号：PCT/JP1997000376
申请日：1997-02-13
申请人： UNITED MEMORIES INC. , NIPPON STEEL SEMICONDUCTOR CORPORATION
发明人： UNITED MEMORIES INC. , NIPPON STEEL SEMICONDUCTOR CORPORATION , JONES, Oscar, F., Jr. , PARRIS, Michael, C.
IPC分类号： G11C07/00
CPC分类号： G11C7/22
摘要： A clock doubler circuit for synchronous DRAMs bases transitions in a derived clock signal DCLKB on transitions in an external clock signal CLKPAD and transitions in internally generated pulses HTIME, LTIME. One-shot circuits provide these pulses. At least one of the one-shots is programmable.
摘要翻译：用于同步DRAM的时钟倍频电路基于外部时钟信号CLKPAD中的转换上的导出时钟信号DCLKB中的转换，并在内部产生的脉冲HTIME，LTIME中转换。单触发电路提供这些脉冲。至少一个单次拍摄是可编程的。

2. 发明授权

EP0742589B1 Bond pad option for integrated circuits 失效
标题翻译：表面粘结集成电路选项
公开(公告)号：EP0742589B1
公开(公告)日：2000-10-25
申请号：EP96107092.7
申请日：1996-05-06
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Parris, Michael , Cordoba, Michael V.
IPC分类号： H01L23/525 , H01L27/118
CPC分类号： H01L24/06 , H01L23/50 , H01L24/03 , H01L24/48 , H01L27/11898 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/85385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099 , H01L2224/85399

3. 发明授权

EP0609497B1 A device and method for maintaining a high voltage for low power applications 失效转让
标题翻译：装置和方法用于维持低功率用途的高电压
公开(公告)号：EP0609497B1
公开(公告)日：1999-07-28
申请号：EP93117388.4
申请日：1993-10-27
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael
IPC分类号： G11C5/14
CPC分类号： G05F3/205 , G05F1/465 , G11C5/14 , G11C5/145 , G11C5/146

4. 发明公开

EP0852381A3 Sense amplifier with local write drivers 失效
标题翻译：放大器，具有本地写驱动程序
公开(公告)号：EP0852381A3
公开(公告)日：1999-07-07
申请号：EP98102694.1
申请日：1993-09-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Hardee, Kim C.
IPC分类号： G11C7/06
CPC分类号： G11C7/1096 , G11C7/065 , G11C7/1078
摘要： A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one (140) connecting the P channel transistors (112, 114) to VCC; the other (142) connecting the N channel transistors (142) to VSS. A read amplifier circuit (150-156) is provided within each sense amplifier and is operated by read control signals (DR, DRB, YR). Internal nodes of the latch of the sense amplifier are coupled by pass transistors (122, 124) that are responsive to column write control signals (YW). Local data write driver transistors (128, 130, 132, 134) are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals (DW, DWB). A relatively wider power line (184) is coupled to the drive transistors (140) to provide VCC thereto, and a narrower line (181) is used to control those first sense amplifier drive transistors (140). Corresponding wide and narrow lines (190, 186) are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines (220, 222; 224, 226) through the use of isolation transistors 232, 234, 238, 240) and a corresponding isolation signal (ISOL, ISOR).

5. 发明授权

EP0602355B1 Fuse programmable voltage down converter 失效转让
标题翻译：熔断线可编程电压降压转换器
公开(公告)号：EP0602355B1
公开(公告)日：1998-12-23
申请号：EP93117387.6
申请日：1993-10-27
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael V. , Hardee, Kim C.
IPC分类号： G05F1/46
CPC分类号： G05F3/205 , G05F1/465 , G11C5/14 , G11C5/145 , G11C5/146 , G11C5/147

6. 发明授权

EP0595050B1 Sense amplifier clock driver 失效转让
标题翻译：时钟驱动器读出放大器
公开(公告)号：EP0595050B1
公开(公告)日：1998-12-16
申请号：EP93115771.3
申请日：1993-09-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Hardee, Kim C.
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065

7. 发明授权

EP0563521B1 Low power DRAM 失效
标题翻译：具有低功耗的DRAM
公开(公告)号：EP0563521B1
公开(公告)日：1998-08-12
申请号：EP93101104.3
申请日：1993-01-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Eaton, Sheffield S. Jr.
IPC分类号： G11C11/407 , G11C11/409
CPC分类号： G11C11/4074

8. 发明授权

EP0608489B1 Low-to-high voltage translator with latch-up immunity 失效转让
标题翻译：低到高的电平转换器具有闭锁强度
公开(公告)号：EP0608489B1
公开(公告)日：1997-12-29
申请号：EP93117027
申请日：1993-10-21
申请人： UNITED MEMORIES INC , NIPPON STEEL SEMICONDUCTOR CO
发明人： HARDEE KIM C , MOBLEY KENNETH J
IPC分类号： G11C11/407 , G11C11/409 , H03K3/356 , H03K5/02 , H03K19/0185 , H03K19/003
CPC分类号： H03K3/356017 , H03K3/356113

9. 发明授权

EP0593105B1 Efficient negative charge pump 失效
标题翻译：负高功率充电泵
公开(公告)号：EP0593105B1
公开(公告)日：1997-05-02
申请号：EP93202506.7
申请日：1993-08-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael V. , Hardee, Kim C.
IPC分类号： H02M3/07 , H02M3/10 , H03L1/00 , H03L5/00 , H03K5/135 , H03K5/02 , G05F3/16
CPC分类号： H02M3/073 , G05F3/205

10. 发明公开

EP0743757A2 Programmable binary/interleave sequence counter 失效
标题翻译：程序员Zählerfürbinäreund verschachtelte Sequenzen
公开(公告)号：EP0743757A2
公开(公告)日：1996-11-20
申请号：EP96107857.3
申请日：1996-05-17
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Jones, Oscar Frederick Jr.
IPC分类号： H03K23/00
CPC分类号： H03K23/004 , G11C8/04
摘要： A counter circuit (10) selectively generates counting sequences in binary and interleave counting modes. A counter (16) is formed by 3 toggle flip-flops (44, 46, 48). The toggle signals are provided by a toggle control circuit (20) which contains logic gates that are enabled or disabled based on the state of a mode select signal (SELECT). In binary mode, output bits are permitted to be used to toggle higher order count stages (46, 48). In interleave mode, the binary toggle signals are blocked, and another counter circuit (18) counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit (20) to toggle inputs of the main counter (16). The other counter circuit (18) can be reset in response to a reset signal (IRESET) applied to a load enable input.
摘要翻译：计数器电路选择性地产生二进制和交错计数模式的计数序列。计数器由3个拨动触发器组成。触发信号由包括基于模式选择信号的状态使能或禁用的逻辑门的触发控制电路提供。在二进制模式下，允许输出位用于切换较高阶计数级。在交错模式下，二进制触发信号被阻塞，另一个计数器电路对交织序列中的触发信号进行计数，该信号由触发控制电路传递以切换主计数器的输入。响应于施加到负载使能输入的复位信号，可以复位另一个计数器电路。

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