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1. 发明申请

WO03017558A3 METHOD AND APPARATUS FOR ENHANCING DATA RATES IN SPREAD SPECTRUM COMMUNICATION SYSTEMS 审中-公开
标题翻译：在扩频通信系统中增强数据速率的方法和设备
公开(公告)号：WO03017558A3
公开(公告)日：2003-05-01
申请号：PCT/US0226961
申请日：2002-08-21
申请人： MORPHICS TECH INC
发明人： JALLOUL LOUAY M A , SHANBHAG ABHIJIT G
IPC分类号： H04B1/707 , H04B1/7103 , H04B1/7105 , H04B1/7107 , H04B1/7115 , H04J11/00 , H04J13/00 , H04J13/12 , H04L27/30 , H04B15/00 , H04K1/00
CPC分类号： H04J13/12 , H04B1/7103 , H04B1/71055 , H04B1/71072 , H04B1/71075 , H04B1/7115 , H04J13/00 , H04J13/0048 , H04J13/0077
摘要： This invention relates to a spread spectrum communication system which enhances the data rate. In accordance with the invention, a high data rate spread spectrum transmitter (100) comprises an encoder (110) for encoding an input bit stream of R bits/second to produce an output bit stream of Rs bits/second, an interleaver (120) for scrambling the bits of the output bit straem of the encoder to produce an interleaved bit stream, a M-ary modulator (130) for modulating the interleaved bit stream, a serial-to-parallel converter (140) to convert the modulated bit stream to a plurality of parallel bit streams, a generator for generating a set of quasi orthogonal functions of a set of Walsh codes, an array of multipliers (150), each multiplier receiving one of the parallel bit streams and multiplying it with a Walsh code or quasi orthogonal function of a Walsh code to produce a spread spectrum bit stream, and a combiner (160) for combining the spread spectrum bit streams from the array of multipliers. Further, in accordance with the invention a high data rate receiver comprises a front end receiver for receiving the spread spectrum signal, a despreader for despreading the signal using a set of Walsh codes or quasi orthogonal function, a multi-user detection block for subtracting interference in the despread signal to form a corrected signal, and a combiner for combining the corrected signals.
摘要翻译：本发明涉及一种增强数据速率的扩频通信系统。根据本发明，高数据速率扩频发射机（100）包括：编码器（110），用于编码R比特/秒的输入比特流以产生R比特/秒的输出比特流;交织器（120）用于加扰编码器的输出比特流的比特以产生交织比特流;用于调制交织比特流的M元调制器（130）;串并转换器（140），用于将经调制的比特流用于产生一组沃尔什码的准正交函数的一个发生器，一个乘法器阵列（150），每个乘法器接收一个并行比特流并将其与沃尔什码相乘或用于产生扩频比特流的沃尔什码的准正交函数和用于组合来自乘法器阵列的扩频比特流的组合器（160）。此外，根据本发明，高数据速率接收机包括用于接收扩频信号的前端接收机，用于使用一组沃尔什码或准正交函数对信号进行解扩的解扩器，用于减去干扰的多用户检测块在去扩展信号中形成校正信号，以及组合器，用于组合校正信号。

2. 发明申请

WO0211404A2 APPARATUS AND METHOD FOR CONFIGURABLE MULTI-DWELL SEARCH ENGINE FOR SPREAD SPECTRUM APPLICATIONS 审中-公开
标题翻译：用于传播频谱应用的可配置多重搜索引擎的装置和方法
公开(公告)号：WO0211404A2
公开(公告)日：2002-02-07
申请号：PCT/US0124330
申请日：2001-07-31
申请人： MORPHICS TECH INC
发明人： RIEKEN KEITH
IPC分类号： H04B1/707 , H04B1/7073 , H04B1/7077 , H04B1/7117 , H04W48/16 , H04W52/00 , H04M
CPC分类号： H04W48/16 , H04B1/70735 , H04B1/70775 , H04B1/7117
摘要： This invention provides a configurable multi-dwell search engine (200) for performing automated efficient searches of a known code sequence space. Inputs from a multi-dwell table (202) and a finger control table (204) are multiplexed by a first multiplexer (206). Output from the first multiplexer is used to generate a threshold comparison signal. The generated threshold comparison signal, the current dwell state signal and inputs from a next dwell look-up table (212) are multiplexed by a second multiplexer (210). The second multiplexer outputs a hard hit signal and an offset control signal.
摘要翻译：本发明提供了一种用于执行已知代码序列空间的自动化有效搜索的可配置多停留搜索引擎（200）。来自多驻留表（202）和手指控制表（204）的输入由第一多路复用器（206）复用。来自第一多路复用器的输出用于产生阈值比较信号。产生的阈值比较信号，当前驻留状态信号和来自下一个停留查找表（212）的输入由第二多路复用器（210）复用。第二多路复用器输出硬命中信号和偏移控制信号。

3. 发明申请

WO0177779A2 VIRTUAL MACHINE INTERFACE FOR HARDWARE RECONFIGURABLE AND SOFTWARE PROGRAMMABLE PROCESSORS 审中-公开
标题翻译：硬件可重构和软件可编程处理器的虚拟机接口
公开(公告)号：WO0177779A2
公开(公告)日：2001-10-18
申请号：PCT/US0111184
申请日：2001-04-05
申请人： MORPHICS TECH INC
发明人： CHEN SONG , HESKY KENNETH M , JOAG RAJU R , MEDLOCK JOEL D , WOODTHORPE CHRISTOPHER C
IPC分类号： G06F9/44 , H04L12/28 , H04W24/02 , H04W88/08 , G06F
CPC分类号： G06F9/44 , H04W24/02 , H04W88/08
摘要： The present invention provides a virtual machine interface (VMI) (307) and an application programming interface (API) (303) usable in conjunction with a reconfigurable wireless network communication apparatus (311). The reconfigurable wireless network communication apparatus comprises a plurality of hardware kernels. The apparatus can be reconfigured to support different or modified communication protocols over time. The VMI (307) comprised a library of software objects. By configuring VMI software objects, a programmer selects the communication protocol used by the reconfigurable wireless network communication apparatus. The API (303) of the present invention provides higher level management of the communication protocol used by a reconfigurable wireless network communication apparatus. The API comprises a library of high level software objets that further abstract hardware details of the apparatus.
摘要翻译：本发明提供了一种可配置可重构无线网络通信设备（311）的虚拟机接口（VMI）（307）和应用编程接口（API）303。可重构无线网络通信装置包括多个硬件内核。该装置可以被重新配置以支持随着时间的不同或修改的通信协议。 VMI（307）包括一个软件对象库。通过配置VMI软件对象，程序员选择可重构无线网络通信设备使用的通信协议。本发明的API（303）提供了由可重构无线网络通信装置使用的通信协议的更高级别的管理。该API包括高级软件对象的库，其进一步抽象该装置的硬件细节。

4. 发明申请

WO0069084A9 REPROGRAMMABLE DIGITAL WIRELESS COMMUNICATION DEVICE AND METHOD OF OPERATING SAME 审中-公开
标题翻译：可复用数字无线通信设备及其操作方法
公开(公告)号：WO0069084A9
公开(公告)日：2002-08-29
申请号：PCT/US0012473
申请日：2000-05-05
申请人： MORPHICS TECH INC
发明人： SUBRAMANIAN RAVI
IPC分类号： H04B1/40 , H04B1/00 , H04B1/28 , H04B1/38
CPC分类号： H04B1/0003 , H04B1/00 , H04B1/005 , H04B1/28
摘要： A digital wireless communication device (100) comprises a software-programmable processor (70), a heterogeneous reconfigurable multiprocessing logic circuit (66), and a bus (52) connecting the software-programmable processor (70) and the heterogeneous reconfigurable multiprocessing logic circuit (66). The heterogeneous reconfigurable multiprocessing logic circuit (66) comprises a set of heterogeneous signal processing kernels and a reconfigurable data router interconnecting the heterogeneous signal processing kernels. The software-programmable processor (70) is selected from a group comprising: a digital signal processor (72) and a central processing unit (74). The architecture provides the ability to reconfigure a single product platform for multiple standards, applications, services, and quality-of service, instead of developing multiple hardware platforms to establish the same collective functionality. The architecture also provides the ability to use software programming techniques to reduce product development time and achieve rapid and comprehensive product customization. The invention extends the performance efficiency of microprocessors and digital signal processors via the augmentation of data path and control paths through a reconfigurable co-processing machine. The reconfigurability of the data path optimizes the performance of the data flow in the algorithms implemented on the processor.
摘要翻译：数字无线通信设备（100）包括软件可编程处理器（70），异构可重新配置多处理逻辑电路（66）和连接软件可编程处理器（70）和异构可重新配置的多处理逻辑电路（66）。异构可重构多处理逻辑电路（66）包括一组异构信号处理内核和互连异构信号处理内核的可重配置数据路由器。软件可编程处理器（70）从包括数字信号处理器（72）和中央处理单元（74）的组中选择。该架构提供了为多个标准，应用程序，服务和服务质量重新配置单个产品平台的能力，而不是开发多个硬件平台来建立相同的集体功能。该架构还提供使用软件编程技术来减少产品开发时间并实现快速和全面的产品定制的能力。本发明通过可重构协同处理机的数据路径和控制路径的增加来扩展微处理器和数字信号处理器的性能效率。数据路径的可重构性优化了在处理器上实现的算法中数据流的性能。

5. 发明申请

WO0068698A9 APPARATUS AND METHOD FOR IMPLEMENTING A WIRELESS SYSTEM-ON-A-CHIP WITH A REPROGRAMMABLE TESTER, DEBUGGER, AND BUS MONITOR 审中-公开
标题翻译：用可重复测试仪，调试器和总线监控器实现无线系统的芯片的装置和方法
公开(公告)号：WO0068698A9
公开(公告)日：2002-06-06
申请号：PCT/US0012472
申请日：2000-05-05
申请人： MORPHICS TECH INC
发明人： RIEKEN KEITH
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G01R31/3187 , G06F11/22 , G06F11/28 , G06F13/00 , H04L12/56
CPC分类号： G01R31/3187 , G01R31/31705 , G01R31/318533 , G01R31/318555 , H04W24/00
摘要： A wireless communication system-on-a-chip (20) comprises a system bus (24), a set of fixed function processors (32) connected to the system bus (24), an embedded processor (28) connected to the system bus (24), and reconfigurable logic (30) connected to the system bus (24). The reconfigurable logic (30) supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.
摘要翻译：一种无线通信系统芯片（20）包括系统总线（24），连接到系统总线（24）的一组固定功能处理器（32），连接到系统总线的嵌入式处理器（28）（24）和连接到系统总线（24）的可重新配置逻辑（30）。可重构逻辑（30）支持操作模式和诊断模式。在操作模式下，系统支持不同的空中接口协议和数据速率。在诊断模式下，系统交替测试系统，调试系统，并监控系统内的总线活动。

6. 发明申请

WO0213400A3 FLEXIBLE PREAMBLE PROCESSING 审中-公开
标题翻译：灵活的前导处理
公开(公告)号：WO0213400A3
公开(公告)日：2002-04-11
申请号：PCT/US0124630
申请日：2001-08-03
申请人： MORPHICS TECH INC
发明人： GOSLIN GREGORY R , BALASUBRAMONIAN VENUGOPAL
IPC分类号： H04B1/707 , H04B1/7075 , H04B1/7077 , H04B1/69
CPC分类号： H04B1/7077 , H04B1/707 , H04B1/70751 , H04B2201/70701 , H04B2201/70707 , H04J3/0611
摘要： An architecture and method for flexible preamble processing is disclosed herein. A preamble processing engine (220) detects a code sequence in input, where the code sequence is a sum of a first code sequence (240) and a second code sequence (244). The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers (300a-300m). The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.
摘要翻译：这里公开了用于灵活的前导码处理的架构和方法。前导码处理引擎（220）检测输入中的码序列，其中码序列是第一码序列（240）和第二码序列（244）的和。前导码处理引擎包括数据输入线，代码输入线，解扩器和多个存储器寄存器（300a-300m）。代码输入选择性地接收第一代码序列或第二代码序列，第一代码序列的周期长于第二代码序列的周期。解扩器连接到数据输入线和代码输入线。解扩器在第一码序列和输入数据之间产生解扩结果。最后，耦合到解扩器的多个存储寄存器每个仅存储一部分解扩结果。

7. 发明申请

WO02054601A9 CHANNEL CODEC PROCESSOR CONFIGURABLE FOR MULTIPLE WIRELESS COMMUNICATIONS STANDARDS 审中-公开
标题翻译：可编程多路无线通信标准的通道编解码处理器
公开(公告)号：WO02054601A9
公开(公告)日：2003-09-18
申请号：PCT/US0149478
申请日：2001-12-28
申请人： MORPHICS TECH INC
发明人： BITTERLICH STEFAN JOHANNES , HOLMES DAVID MORRIS
IPC分类号： H03M13/09 , H03M13/23 , H03M13/29 , H03M13/41 , H04L1/00 , H03M3/03 , H04B1/38 , H04L27/06
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/29 , H03M13/2957 , H03M13/41 , H03M13/6511 , H03M13/6569 , H04L1/0041 , H04L1/005 , H04L1/0066
摘要： A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor (200). In particular, the reconfigurable channel CODEC processor includes processor cores (210, 250) and algorithm-specific kernels (212, 214, 216, 252, 254, 256) that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects (230, 270) between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.
摘要翻译：公开了一种用于无线通信系统的可重构信道CODEC（编码器和解码器）处理器。通道CODEC处理器（200）提供高度的用户可编程性和可重构性。特别地，可重构信道CODEC处理器包括处理器核（210,250）和算法特定的内核（212,214,216,252,254,256），其包含为执行预定但用户可配置的解码和编码而定制的逻辑电路算法。处理器核心和特定于算法的内核之间的互连（230,270）也是用户可配置的。因此，可以为许多不同的无线通信标准重新配置相同的硬件。

8. 发明申请

WO0069192A9 METHOD OF PROFILING DISPARATE COMMUNICATIONS AND SIGNAL PROCESSING STANDARDS AND SERVICES 审中-公开
标题翻译：分析通信和信号处理标准和服务的方法
公开(公告)号：WO0069192A9
公开(公告)日：2002-06-13
申请号：PCT/US0012474
申请日：2000-05-05
申请人： MORPHICS TECH INC
发明人： SUBRAMANIAN RAVI
IPC分类号： H04B1/40 , H04B14/00 , H04J99/00 , H04L29/06 , H04L29/08 , H04Q7/32
CPC分类号： H04L29/06 , H04L69/32 , H04W48/18
摘要： A method for profiling disparate communications and signal processing standards begins with selection of a set of standards for analysis (32). Next, functions performed by the set of standards are identified (34) and ranked (36). A set of high ranked functions are then implemented as kernels (38), the set of kernals forming a programmable processor that enables implementations of any one of the set of communications and signal processing standards (42).
摘要翻译：分析不同通信和信号处理标准的方法从选择一组分析标准开始（32）。接下来，识别由该组标准执行的功能（34）和等级（36）。然后，将一组高排名的功能实现为内核（38），该组内核形成可执行通信和信号处理标准（42）中的任何一个的可编程处理器。

9. 发明申请

WO0069085A9 PROGRAMMABLE DIGITAL INTERMEDIATE FREQUENCY TRANSCEIVER 审中-公开
标题翻译：可编程数字中频收发器
公开(公告)号：WO0069085A9
公开(公告)日：2002-06-13
申请号：PCT/US0012475
申请日：2000-05-05
申请人： MORPHICS TECH INC
发明人： SUBRAMANIAN RAVI
IPC分类号： H04L27/38 , H03C3/40 , H03D3/00 , H03D7/16 , H04B1/04 , H04B1/06 , H04B1/28 , H04L27/22 , H04B1/38
CPC分类号： H04B1/0017 , H03C3/40 , H03D3/007 , H03D7/165 , H04B1/001 , H04B1/28
摘要： A monolithic CMOS programmable digital intermediate frequency receiver (20) includes a programmable memory (29), a clock generator (26), a sigma delta converter (22), a digital downconverter (24), and a decimation filter network (28). The programmable memory (29) receives and stores a first value representative of a programmable parameter k and a second value representative of programmable parameter N. Coupled to the programmable memory (29), the clock generator (26) generates a first clock signal, a second clock signal and a third clock signal. The first clock signal has a first frequency, f1, the second clock signal has a second frequency approximately equal to f1/k and the third clock signal has a third frequency approximately equal to f1/N. The sigma delta converter (22), the digital downconverter (24) and the decimation filter network (28) use the respective first, second and third clock signals to generate the respective set of digital signals.
摘要翻译：单片CMOS可编程数字中频接收器（20）包括可编程存储器（29），时钟发生器（26），Σ-Δ转换器（22），数字下变频器（24）和抽取滤波器网络（28）。可编程存储器（29）接收并存储表示可编程参数k的第一值和表示可编程参数N的第二值。耦合到可编程存储器（29），时钟发生器（26）产生第一时钟信号，第二时钟信号和第三时钟信号。第一时钟信号具有第一频率f1，第二时钟信号具有大约等于f1 / k的第二频率，并且第三时钟信号具有大约等于f1 / N的第三频率。 Σ-Δ转换器（22），数字下变频器（24）和抽取滤波器网络（28）使用相应的第一，第二和第三时钟信号来产生相应的数字信号组。

10. 发明申请

WO0156199A8 METHOD AND APPARATUS FOR PROCESSING A SECONDARY SYNCHRONIZATION CHANNEL IN A SPREAD SPECTRUM SYSTEM 审中-公开
标题翻译：用于在传播频谱系统中处理二次同步信道的方法和装置
公开(公告)号：WO0156199A8
公开(公告)日：2002-02-07
申请号：PCT/US0103004
申请日：2001-01-29
申请人： MORPHICS TECH INC
发明人： JHA UMA
IPC分类号： H04B1/707 , H04B1/7073 , H04B1/708 , H04B1/709 , H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： H04B1/708 , H04B1/707 , H04B1/70735 , H04B1/709
摘要： A method and apparatus for processing a secondary synchronization channel (222a) in a spread spectrum system is disclosed herein. The method includes several steps, the first of which is to receive a first input data (250) at a correlator. Next, a first code sequence of a code group (242) is received at the correlator. The first correlator then correlates the first input data with the first code sequence. Afterward, a second code sequence is received at the correlator. This time, the first input data is correlated with the second code sequence. Correlation of both the first code sequence and the second code sequence occurs prior to receiving a second input data. Lastly, correlation results (241) from the first correlator are compared with a threshold value using a threshold detector (244).
摘要翻译：本文公开了一种用于处理扩展频谱系统中的辅同步信道（222a）的方法和装置。该方法包括几个步骤，第一步是在相关器处接收第一输入数据（250）。接下来，在相关器处接收代码组（242）的第一代码序列。然后，第一相关器将第一输入数据与第一代码序列相关联。之后，在相关器处接收第二代码序列。这一次，第一输入数据与第二代码序列相关。第一代码序列和第二代码序列的相关性在接收第二输入数据之前发生。最后，使用阈值检测器将来自第一相关器的相关结果（241）与阈值进行比较（244）。

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