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1. 发明授权

US5922217A Method for correcting defects in a phase shift mask 失效
标题翻译：用于校正相移掩模中的缺陷的方法
公开(公告)号：US5922217A
公开(公告)日：1999-07-13
申请号：US859261
申请日：1997-05-20
申请人： Jun Seok Lee
发明人： Jun Seok Lee
IPC分类号： G03F1/30 , G03F1/68 , G03F1/72 , G03F1/80 , H01L21/027 , B44C1/22
CPC分类号： G03F1/72 , G03F1/26
摘要： A method for correcting defects in a phase shift mask is disclosed. The method includes the steps of: forming an etch stopper layer and a phase shift layer on a substrate in succession; forming light shielding layer patterns on the phase shift layer, the light shielding layer patterns having a plurality of opened regions; defining phase shift regions on selected regions of the phase shift layer in the opened regions; selectively removing the phase shift layer in the phase shift regions to a thickness required for phase shifting; and eliminating a defect by simultaneous further etching the same amount of material from the defective phase shift layer and an adjacent open region. This corrects the defect by converting the defective phase shift region to a non-phase-shift region and converting the adjacent open region into a phase shift region.
摘要翻译：公开了一种用于校正相移掩模中的缺陷的方法。该方法包括以下步骤：在衬底上依次形成蚀刻停止层和相移层; 在所述相移层上形成遮光层图案，所述遮光层图案具有多个开放区域; 在所述开放区域中定义所述相移层的选定区域上的相移区域; 选择性地将相移区域中的相移层去除为相移所需的厚度; 并且通过同时进一步从有缺陷的相移层和相邻的开放区域进一步蚀刻相同量的材料来消除缺陷。这通过将缺陷相移区域转换为非相移区域并将相邻的开放区域转换为相移区域来校正缺陷。

2. 发明授权

US5818087A Electrostatic-discharge protecting circuit and method 失效
标题翻译：静电放电保护电路及方法
公开(公告)号：US5818087A
公开(公告)日：1998-10-06
申请号：US747659
申请日：1996-11-13
申请人： Hyeok Jae Yee
发明人： Hyeok Jae Yee
IPC分类号： H01L21/822 , H01L23/60 , H01L27/02 , H01L27/04 , H01L27/092 , H01L23/62
CPC分类号： H01L27/0251 , H01L27/0925 , Y10S438/981
摘要： An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the electrostatic-discharge protecting circuit and internal circuit, which are formed within a given radius in the range of about 350.mu.m to about 1000.mu.m from the electrostatic-discharge protecting circuit, is thicker than the thickness of gate insulating layers of active devices formed outside the radius.
摘要翻译：半导体器件的静电放电（ESD）保护电路可防止通过输入或输出焊盘施加到内部电路的ESD的损坏。在距离静电放电保护电路约350μm至约1000μm范围内的给定半径内形成的静电放电保护电路和内部电路的各有源器件的各栅极绝缘层的厚度，比形成在半径外的有源器件的栅极绝缘层的厚度厚。

3. 发明授权

US5892722A Column selection circuit 失效
标题翻译：列选择电路
公开(公告)号：US5892722A
公开(公告)日：1999-04-06
申请号：US126737
申请日：1998-07-31
申请人： Seong Jin Jang , Young Hyun Jun , Sung Wook Kim , Tae Hoon Kim
发明人： Seong Jin Jang , Young Hyun Jun , Sung Wook Kim , Tae Hoon Kim
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/10 , G11C11/4096
摘要： A column selection circuit is disclosed, in which a layout area is minimized by reducing the number of data bus lines and sensing speed characteristic is improved by reducing sensing time of a bit line. In a memory for transmitting data stored in a memory cell to a main sensing amplifier through a bit line and a bit bar line and storing the data output from the main sensing amplifier in the memory cell through the bit line and the bit bar line, the column selection circuit includes an equalizer for equalizing the bit line and the bit bar line, a bit line sensing amplifier for compensating signal voltage levels of the bit line and the bit bar line as a word line is selected, first and second enable signal output portions for outputting enable signals to operate the bit line sensing amplifier, a data bus line and a data bus bar line for transmitting the data transmitted to the bit line and the bit bar line from the memory cell to the main sensing amplifier, and transmitting the data output from the main sensing amplifier to the bit line and the bit bar line, a data transmission portion for selectively transmitting the data of the data bus line and data bus bar line and the data of the bit line and bit bar line between the respective lines in response to a column selection signal, a control signal for reading and a write enable signal, and a precharge level adjusting portion for adjusting precharge level of the data bus line and the data bus bar line.
摘要翻译：公开了一种列选择电路，其中通过减少数据总线的数量使布局面积最小化，并且通过减少位线的检测时间来提高感测速度特性。在用于通过位线和位线将存储在存储单元中的数据存储到主感测放大器的存储器中，并且通过位线和位线将存储器单元中输出的从主感测放大器输出的数据存储起来，列选择电路包括用于均衡位线和位线的均衡器，选择用于补偿位线和位线的信号电压电平的位线检测放大器，第一和第二使能信号输出部分用于输出用于操作位线感测放大器的使能信号，数据总线和数据总线条线，用于将从存储器单元发送到位线和位线的数据发送到主感测放大器，并且发送数据从主感测放大器输出到位线和位线，数据传输部分，用于选择性地发送数据总线和数据总线条的数据以及b的数据响应于列选择信号，用于读取的控制信号和写使能信号，在各行之间的行和位条线以及用于调整数据总线和数据总线条线的预充电电平的预充电电平调整部分。

4. 发明授权

US5965920A Input protection circuit 失效
标题翻译：输入保护电路
公开(公告)号：US5965920A
公开(公告)日：1999-10-12
申请号：US957331
申请日：1997-10-24
申请人： Yang-Soo Sung
发明人： Yang-Soo Sung
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L27/02 , H01L27/06 , H01L23/62 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0255 , H01L27/0259
摘要： An input protection circuit which makes it possible to protect an internal circuit with respect to withstanding an electro-static charge by forming multiple discharge loops by connecting each input pad via an input protection circuit. The circuit includes a plurality of pads formed on a P well within a substrate, first discharge paths formed between neighboring pads, and a second discharge path formed between the pads and circuit ground.
摘要翻译：一种输入保护电路，其可以通过经由输入保护电路连接每个输入焊盘来形成多个放电回路来保护内部电路相对于承受静电电荷。电路包括形成在衬底内的P阱上的多个焊盘，在相邻焊盘之间形成的第一放电路径，以及形成在焊盘和电路接地之间的第二放电路径。

5. 发明授权

US5959321A DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion 失效
标题翻译：基本组织单元的DRAM矩阵，每个具有六边形平面部分的一对电容器
公开(公告)号：US5959321A
公开(公告)日：1999-09-28
申请号：US901876
申请日：1997-07-29
申请人： Chang Jae Lee , Won Suck Yang , Kong Hee Park
发明人： Chang Jae Lee , Won Suck Yang , Kong Hee Park
IPC分类号： G11C11/34 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10844 , H01L27/10805
摘要： A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.
摘要翻译：动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。每个电容器对具有第一电容器和其中的第二电容器之一。每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

6. 发明授权

US5817367A Method of forming a thin film of copper 失效
标题翻译：形成铜薄膜的方法
公开(公告)号：US5817367A
公开(公告)日：1998-10-06
申请号：US772290
申请日：1996-12-23
申请人： Soung Soon Chun , Chong Ook Park , Dong Won Kim , Won Jun Lee , Sa Kyun Rha , Kyung Il Lee
发明人： Soung Soon Chun , Chong Ook Park , Dong Won Kim , Won Jun Lee , Sa Kyun Rha , Kyung Il Lee
IPC分类号： C23C16/18 , H01L21/28 , H01L21/285
CPC分类号： C23C16/18
摘要： A method of forming a thin film of copper on a substrate includes a first step of conducting a chemical vapor deposition (CVD) process using a metal organic (MO) source while applying a first bias voltage to the surface of the substrate and a second step of conducting a chemical vapor deposition process using a metal organic source while applying a second bias voltage to the substrate, wherein the second bias voltage is opposite in polarity to the first bias voltage. The process may include a third step of conducting a chemical vapor deposition process using a metal organic source while applying a third bias voltage to the substrate, where the third bias voltage has the same polarity as the first bias voltage.
摘要翻译：在基板上形成铜薄膜的方法包括：第一步骤，使用金属有机（MO）源进行化学气相沉积（CVD）工艺，同时向衬底的表面施加第一偏压，第二步骤使用金属有机源进行化学气相沉积工艺，同时向衬底施加第二偏置电压，其中第二偏压与第一偏置电压极性相反。该方法可以包括第三步骤，其中使用金属有机源进行化学气相沉积工艺，同时向衬底施加第三偏置电压，其中第三偏置电压具有与第一偏置电压相同的极性。

7. 发明授权

US5931349A Viscous fluid discharging apparatus for manufacturing semiconductors having a removable bubble capturing portion 失效
标题翻译：用于制造具有可移除气泡捕获部分的半导体的粘性流体排放装置
公开(公告)号：US5931349A
公开(公告)日：1999-08-03
申请号：US644011
申请日：1996-05-09
申请人： Seung-Seok Yoo
发明人： Seung-Seok Yoo
IPC分类号： B05C5/00 , B01D19/00 , B05C11/10 , B67D7/76 , G03F7/16 , H01L21/027 , B67D5/06
CPC分类号： B67D7/763 , B01D19/0031 , G03F7/16 , Y10T137/3003
摘要： A viscous fluid discharging apparatus is provided for removing air bubbles introduced during the passing of the viscous fluid before being supplied to the substrate. A viscous fluid discharging apparatus according to the present invention includes a viscous fluid storing container, a viscous fluid supplying pump, a viscous fluid filter, and a viscous fluid discharging mechanism provided with a final air bubble filtering means. The fluid material discharging mechanism includes a connecting portion formed on an end of a temperature adjusting mechanism connected to an outlet of the fluid material supplying pump, and a discharging gun. The discharging gun has a sealed joining portion for being sealed and joined to the connecting portion, an air bubble capturing portion for capturing air bubbles from within the viscous fluid, and a viscous fluid path for moving the viscous fluid to an outlet in a sealed state.
摘要翻译：提供了一种粘性流体排放装置，用于去除在粘性流体通过之前引入的气泡，然后供给到基底。根据本发明的粘性流体排放装置包括粘性流体储存容器，粘性流体供应泵，粘性流体过滤器和设置有最终气泡过滤装置的粘性流体排放机构。流体材料排出机构包括形成在连接到流体供给泵的出口的温度调节机构的端部上的连接部分和排放枪。排放枪具有用于密封并接合到连接部分的密封接合部分，用于从粘性流体内捕获气泡的气泡捕获部分和用于将粘性流体以密封状态移动到出口的粘性流体路径。

8. 再颁专利

USRE36097E Semiconductor package for a semiconductor chip having centrally located bottom bond pads 失效
标题翻译：具有中心位置的底部接合焊盘的半导体芯片的半导体封装
公开(公告)号：USRE36097E
公开(公告)日：1999-02-16
申请号：US748460
申请日：1996-11-08
申请人： Gi Bon Cha
发明人： Gi Bon Cha
IPC分类号： H01L23/28 , H01L23/12 , H01L23/31 , H01L23/495 , H01L23/50 , H01L23/48
CPC分类号： H01L24/06 , H01L23/3107 , H01L23/4951 , H01L23/50 , H01L2224/04042 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L2224/48699 , H01L2224/49109 , H01L2224/49171 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/181 , Y10T29/49121 , Y10T29/49146 , Y10T29/49172
摘要： A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
摘要翻译：一种半导体封装，其具有不从封装突出但仅暴露于外部的外引线。半导体封装包括半导体芯片，其在其底表面的中心部分处形成有多个接合焊盘，引线框架包括分别连接到用于输入/输出接合焊盘的接合焊盘的引线和连接到电源的母线接合焊盘的焊盘，用于将引线的内引线和母线的内引线连接到形成有接合焊盘的半导体芯片的底表面的绝缘粘合剂，用于电连接引线的内引线的金属线和内引线母线的引线分别连接到接合焊盘，以及模制化合物，其包围半导体芯片组件，引线框架的外引线暴露于外部。胶合带在成型过程之后被去除。

9. 发明授权

US5834372A Pretreatment of semiconductor substrate 失效
标题翻译：半导体衬底预处理
公开(公告)号：US5834372A
公开(公告)日：1998-11-10
申请号：US571052
申请日：1995-12-12
申请人： Young Chong Lee
发明人： Young Chong Lee
IPC分类号： C30B25/16 , C23C14/02 , C23C14/06 , C23C16/02 , C23C16/08 , C23C16/14 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/44
CPC分类号： H01L21/28556 , C23C16/02 , C23C16/08
摘要： A method for pretreating a semiconductor surface, comprising the steps of: placing a titanium nitride substrate in a reaction chamber and subjecting the reaction chamber to vacuum; purging the reaction chamber with an inert gas selected from the group consisting of N.sub.2, Ar and He and evacuating the reaction chamber into 1 mTorr or lower; treating the surface of the titanium nitride substrate with a reaction gas comprising WF; charging a reducing gas and a source gas for deposition material to form a thin film on the titanium nitride substrate, by which the nucleation rate of deposition material and the number of nucleation sites on the substrate can be increased and a thin film with a uniform thickness and high density can be formed on the substrate.
摘要翻译：一种用于预处理半导体表面的方法，包括以下步骤：将氮化钛衬底放置在反应室中并对反应室进行真空; 用选自N2，Ar和He的惰性气体吹扫反应室，并将反应室抽空至1mTorr以下; 用包含WF的反应气体处理氮化钛衬底的表面; 在氮化钛衬底上填充还原气体和源气体用于沉积材料以形成薄膜，通过该薄膜可以增加沉积材料的成核速率和衬底上的成核位置的数量以及厚度均匀的薄膜并且可以在基板上形成高密度。

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