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1. 发明申请

WO02103667A9 SIMPLE MATRIX LIQUID CRYSTAL DRIVE METHOD AND APPARATUS 审中-公开
标题翻译：简单矩阵液晶驱动方法和装置
公开(公告)号：WO02103667A9
公开(公告)日：2003-10-02
申请号：PCT/JP0205913
申请日：2002-06-13
申请人： KAWASAKI MICROELECTRONICS INC , SAKO NORIMITSU , KITAYAMA HIDEYUKI
发明人： SAKO NORIMITSU , KITAYAMA HIDEYUKI
IPC分类号： G09G3/20 , G09G3/36 , G02F1/133
CPC分类号： G09G3/3625 , G09G3/2014 , G09G3/2018 , G09G3/2025 , G09G3/2077 , G09G3/3692 , G09G2320/0233 , G09G2320/0247 , G09G2320/0261 , G09G2320/0613 , G09G2330/021
摘要： A simple matrix liquid crystal drive method and apparatus, wherein Y (odd number not smaller than 7) rows of row electrodes are simultaneously selected, the Y-bit row selection vector representing the selection pattern of the Y rows of row electrodes is exclusively OR-ed for each bit with the Y-bit ON/OFF display data representing the display pattern of column electrodes, the exclusive ORs are added for each bit, the voltage levels at the column electrodes are selected according to the result of the addition from X voltage levels expressed by [2 x i - (X - 1)] x Vc (i is an integer from 0 to (X-1)) where X = (Y + 1)/2, and Vc is the voltage that is 1/(X - 1) of the maximum voltage at the row electrodes, and the simple matrix liquid crystal is driven by the selected voltages. This method and apparatus prevent the frame response phenomenon of the high-speed liquid crystal and realize high-contrast display, low-voltage drive, low power consumption, and reduction in the chip size.
摘要翻译：同时选择Y行（奇数不少于7行）的简单矩阵液晶驱动方法和装置，表示行电极的Y行的选择图案的Y位行选择矢量仅为OR- 对于每个位，对于表示列电极的显示图案的Y位ON / OFF显示数据，对于每个位添加异或，根据从X电压的相加结果选择列电极处的电压电平其中X =（Y + 1）/ 2，Vc是电压为1 /（（x-1））x Vc（i是从0到（X-1）的整数） X-1），并且简单矩阵液晶由所选择的电压驱动。该方法和装置防止高速液晶的帧响应现象，实现高对比度显示，低电压驱动，低功耗，降低芯片尺寸。

2. 发明专利

JP2013051613A Reception apparatus 有权
标题翻译：接收装置
公开(公告)号：JP2013051613A
公开(公告)日：2013-03-14
申请号：JP2011189453
申请日：2011-08-31
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： YAMASHITA KAZUNORI
IPC分类号： H04L7/00 , H04L7/08
摘要： PROBLEM TO BE SOLVED: To provide a reception apparatus that is less expensive owing to a reduced circuit scale of a pattern detection circuit.SOLUTION: The reception apparatus includes: a conversion circuit for converting serial data including an M-bit long specific pattern to N-bit (N
摘要翻译：要解决的问题：提供一种由于图案检测电路的电路规模减小而成本较低的接收装置。解决方案：接收装置包括：转换电路，用于将包括M位长特定模式的串行数据转换为N位（N

3. 发明专利

JP2012220926A Image processor 有权
标题翻译：图像处理器
公开(公告)号：JP2012220926A
公开(公告)日：2012-11-12
申请号：JP2011090055
申请日：2011-04-14
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： U KAN
IPC分类号： G09G5/00 , G09G3/20 , G09G5/391 , H04N7/01
CPC分类号： H04N7/0105 , G09G5/005 , G09G5/39 , G09G2320/106 , G09G2340/02 , G09G2340/0428 , G09G2340/0435 , G09G2350/00 , H04N7/0132 , H04N7/014
摘要： PROBLEM TO BE SOLVED: To provide an image processor capable of reducing a memory capacity.SOLUTION: An image processor comprises: a memory control circuit for receiving pixel data for multiple frames in order of the frames, and storing it in a frame memory; an image processing circuit for using a high-order bit portion of the pixel data stored in the frame memory to generate processed pixel data; and an output circuit for outputting the processed pixel data. The memory control circuit includes; a separation circuit for separating the pixel data into the high-order bit portion and a low-order bit portion; and a low-order bit processing circuit for storing the low-order bit portion in the frame memory. The low-order bit processing circuit divides pixels of each frame into n sets (n is an integer equal to or greater than 2), and stores in the frame memory the separated low-order bit portion only of the pixel data for corresponding one set of pixels among the divided n sets of pixels, in a period for receiving the pixel data in sequential n frames.
摘要翻译：要解决的问题：提供能够降低存储容量的图像处理器。解决方案：图像处理器包括：存储器控制电路，用于按照帧的顺序接收多个帧的像素数据，并将其存储在帧存储器中; 用于使用存储在所述帧存储器中的像素数据的高位位部分来生成经处理的像素数据的图像处理电路; 以及用于输出经处理的像素数据的输出电路。存储器控制电路包括：分离电路，用于将像素数据分离成高阶位部分和低位位部分; 以及用于将低位比特部分存储在帧存储器中的低位比特处理电路。低位位处理电路将每帧的像素分成n组（n是等于或大于2的整数），并且在帧存储器中仅存储对应一组的像素数据的分离的低位位部分在用于在顺序n帧中接收像素数据的周期中，在分割的n个像素组中的像素的像素。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012044042A Semiconductor integrated circuit and semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路和半导体集成电路器件
公开(公告)号：JP2012044042A
公开(公告)日：2012-03-01
申请号：JP2010185069
申请日：2010-08-20
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： KIRYU HIROYOSHI
IPC分类号： H01L23/12 , H01L21/822 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L24/73 , H01L2224/48227 , H01L2224/49171 , H01L2224/73257 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a semiconductor integrated circuit device which can stably supply power source voltage.SOLUTION: In a semiconductor integrated circuit 40, a core circuit operating when a first power is supplied is formed on a core region on a surface of a semiconductor substrate and an I/O circuit operating when a second power is supplied is formed on an I/O region outside the core region on the surface of the semiconductor substrate The semiconductor integrated circuit 40 comprises a through via 51 supplying the first power in the semiconductor substrate so as to penetrate the semiconductor substrate and a pad 46 supplying the second power on the I/O region on the surface of the semiconductor substrate.
摘要翻译：要解决的问题：提供一种可以稳定地提供电源电压的半导体集成电路和半导体集成电路器件。解决方案：在半导体集成电路40中，当在半导体衬底的表面上的芯区域上形成提供第一电力时工作的核心电路，并且形成在供应第二电力时工作的I / O电路在半导体衬底的表面上的芯区域外部的I / O区域上。半导体集成电路40包括：通孔51，其供给半导体衬底中的第一电力以穿透半导体衬底;以及焊盘46，其提供第二电力在半导体衬底的表面上的I / O区域上。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2011145084A Semiconductor device, board, and test method 审中-公开
标题翻译：半导体器件，板和测试方法
公开(公告)号：JP2011145084A
公开(公告)日：2011-07-28
申请号：JP2010003873
申请日：2010-01-12
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： MATSUO NAOYA
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a board performing a function test of a semiconductor device having an output buffer with large delay at a high-speed.
SOLUTION: The board for testing a semiconductor device outputting an output signal in synchronization with a clock signal includes an input terminal inputting the output signal, an output terminal outputting the output signal to a comparator of a semiconductor test apparatus, and a charging circuit connected to the output terminal. The charging circuit charges the output terminal to a prescribed electric potential during a period of time in which the clock signal is at one level.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种执行具有高速延迟大的输出缓冲器的半导体器件的功能测试的板。解决方案：用于测试与时钟信号同步输出输出信号的半导体器件的板包括输入输入信号的输入端，将输出信号输出到半导体测试装置的比较器的输出端和充电电路连接到输出端子。在时钟信号处于一个电平的时间段期间，充电电路将输出端子充电到规定的电位。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011019175A Saturation adjusting circuit 有权
标题翻译：饱和调节电路
公开(公告)号：JP2011019175A
公开(公告)日：2011-01-27
申请号：JP2009163839
申请日：2009-07-10
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： HASHIMOTO YORIYUKI
IPC分类号： H04N1/46 , G06T1/00 , H04N1/60 , H04N9/68
摘要： PROBLEM TO BE SOLVED: To reduce circuit scale of a saturation adjusting circuit for adjusting only the saturation of a color image represented in an RGB color space.SOLUTION: A saturation adjusting circuit is configured to receive inputs of values of RGB components of a color image in an RGB color space and to output adjusted RGB components, for which only the saturation in an HSL color space has been adjusted, and includes a maximum and minimum value detection circuit and a corrected RGB component generation circuit. The maximum and minimum value detection circuit detects maximum and minimum values in the RGB components. The corrected RGB component generation circuit outputs, as corrected RGB components, results of performing logical operation on each of the RGB components using a sum of the maximum and minimum values, the respective components and a saturation adjustment coefficient.
摘要翻译：要解决的问题：减少饱和度调节电路的电路规模，以仅调整RGB颜色空间中表示的彩色图像的饱和度。解调：饱和度调整电路被配置为接收彩色图像的RGB分量的值的输入在RGB颜色空间中，并且输出仅对HSL颜色空间中的饱和度进行了调整的经调整的RGB分量，并且包括最大值和最小值检测电路以及校正后的RGB分量产生电路。最大值和最小值检测电路检测RGB分量中的最大值和最小值。校正的RGB分量生成电路使用最大值和最小值，各个分量和饱和度调整系数的和，输出作为校正的RGB分量对每个RGB分量执行逻辑运算的结果。

7. 发明专利

JP2010268302A Code conversion circuit and counter 有权
标题翻译：代码转换电路和计数器
公开(公告)号：JP2010268302A
公开(公告)日：2010-11-25
申请号：JP2009118981
申请日：2009-05-15
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： YAMASHITA KAZUNORI
IPC分类号： H03M7/16 , H03K23/58
摘要： PROBLEM TO BE SOLVED: To provide a code conversion circuit which is reduced in the effort of design and also is suppressed in the increase of circuit scale, and also to provide a counter.
SOLUTION: Pseudo gray codes in which each numeric value from a numeric value zero to a numeric value 13 is expressed by 5 bits, and all humming distances between the adjacent numeric values and between the numeric value 13 and the numeric value zero are 1, are converted into binary codes by a first code conversion circuit 12, counted up by an addition circuit 13, converted into pseudo gray codes corresponding to the counted-up binary codes by a second code conversion circuit 14, and stored in a first register 11.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供减少设计努力的代码转换电路，并且在电路规模的增加中也被抑制，并且还提供计数器。解决方案：伪灰度代码，其中从数字值零到数值13的每个数值由5位表示，相邻数值之间以及数值13与数值零之间的所有蜂鸣距离为 1由第一代码转换电路12转换成二进制代码，由加法电路13向上计数，由第二代码转换电路14转换成对应于计数的二进制代码的伪灰度代码，并存储在第一寄存器 11.版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010268287A Optical subscriber line terminating device 审中-公开
标题翻译：光电订户终端设备
公开(公告)号：JP2010268287A
公开(公告)日：2010-11-25
申请号：JP2009118777
申请日：2009-05-15
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： KAMISHIRO SATORU
IPC分类号： H04L12/44 , H04L13/08
摘要： PROBLEM TO BE SOLVED: To provide an ONT (Optical Network Termination) constituted so as to once store communication data into a memory, which avoids loss of data in an uplink direction and transmission of invalid data.
SOLUTION: The ONT includes: the memory which stores transmission/reception data; a first interface which writes first data received from an OLT in the memory, and reads second data received from a user terminal from the memory and transmits the second data to the OLT; a second interface which writes the second data in the memory, and reads the first data from the memory and transmits the first data to the user terminal; a controller which arbitrates access from each interface to the memory; and a band adjustment circuit which adjusts assignment of each memory band so as to give priority to transmission/reception of the second data over transmission/reception of the first data, based on band information of transmission data extracted from data to the ONT to be transmitted per unit time.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种ONT（光网络终端），其被构造成将通信数据一次存储到存储器中，这避免了上行链路方向上的数据丢失和无效数据的传输。解决方案：ONT包括：存储发送/接收数据的存储器; 第一接口，其将从OLT接收的第一数据写入存储器，并从存储器读取从用户终端接收的第二数据，并将第二数据发送到OLT; 第二接口，将第二数据写入存储器，并从存储器读取第一数据，并将第一数据发送给用户终端; 控制器，其仲裁从每个接口到存储器的访问; 以及频带调整电路，其基于从要发送的ONT的数据提取的发送数据的频带信息，调整每个存储带的分配，以便优先于通过第一数据的发送/接收来发送/接收第二数据每单位时间。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2010250486A Network repeater apparatus 审中-公开
标题翻译：网络重装设备
公开(公告)号：JP2010250486A
公开(公告)日：2010-11-04
申请号：JP2009098131
申请日：2009-04-14
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： FURUKAWA TAKANORI
IPC分类号： G06F12/02
摘要： PROBLEM TO BE SOLVED: To provide a network repeater apparatus for achieving processing corresponding to attributes without preparing an exclusive storage region for each attribute by using an associative memory.
SOLUTION: The network repeater apparatus includes a CAM in which an entry corresponding to received data is registered and a control part for controlling the operation of the CAM, and the entry includes attribute information showing the attributes of data and page information for managing the processing order of the data of the same attributes, and the control part obtains the address of the empty entry of the CAM in registering a new entry in the CMA, and when the obtained address is larger than the address of the final entry of the same attributes as the attribute information of the new entry, the page information of the new entry is defined as the same page number as the page information of the final entry, and when the address is smaller, the page information of the new entry is defined as a page number different from the page information of the final entry, and the new entry is added to the address of the obtained empty entry.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种网络中继器装置，用于通过使用关联存储器为每个属性准备专用存储区域来实现与属性相对应的处理。解决方案：网络中继器装置包括CAM，其中登记与接收到的数据相对应的条目，以及用于控制CAM的操作的控制部分，并且该条目包括表示数据属性的属性信息和用于管理的页面信息相同属性的数据的处理顺序，并且控制部分在CMA中注册新条目时获得CAM的空条目的地址，并且当所获得的地址大于所述CMA的最终条目的地址时与新条目的属性信息相同的属性，新条目的页面信息被定义为与最终条目的页面信息相同的页码，并且当地址较小时，新条目的页面信息被定义作为与最终条目的页面信息不同的页码，并且将新条目添加到所获得的空条目的地址。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010216810A Temperature detection circuit 有权
标题翻译：温度检测电路
公开(公告)号：JP2010216810A
公开(公告)日：2010-09-30
申请号：JP2009060476
申请日：2009-03-13
申请人： Kawasaki Microelectronics Inc , 川崎マイクロエレクトロニクス株式会社
发明人： KISHIMOTO NAOYA
IPC分类号： G01K7/00 , G01K7/20
摘要： PROBLEM TO BE SOLVED: To detect whether the value of temperature is optimum, or in which direction the temperature deviates from the optimum value.
SOLUTION: A temperature detection circuit includes: a transistor MP1 where a voltage V1 inside a BGR circuit 1 is input to its gate, and the current of the output stage of the BGR circuit is mirrored; a transistor MP2 where a voltage V2 inside a Gm-constant circuit 2 is input to its gate and the current of the output stage of the Gm-constant circuit 2 is mirrored; a resistor R1 connected to the drain of the transistor MP1; resistors R2 and R3 connected in series to the drain of the transistor MP2; a comparator 3 for comparing the voltage Va of a node N1 with the voltage Vb of a node N2; a comparator 4 for comparing the voltage Va of the node N1 with the voltage Vc of a node N3. From the combination of the output voltages of the comparators 3 and 4, it is determined whether the current temperature is a target value, or is lower than or higher than the value.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：检测温度值是最佳值还是在哪个方向温度偏离最佳值。解决方案：温度检测电路包括：晶体管MP1，其中BGR电路1内的电压V1被输入到其栅极，并且BGR电路的输出级的电流被镜像; Gm常数电路2内的电压V2被输入到其栅极并且Gm常数电路2的输出级的电流被镜像的晶体管MP2; 连接到晶体管MP1的漏极的电阻器R1; 电阻器R2和R3串联连接到晶体管MP2的漏极; 用于将节点N1的电压Va与节点N2的电压Vb进行比较的比较器3; 用于将节点N1的电压Va与节点N3的电压Vc进行比较的比较器4。从比较器3和4的输出电压的组合，确定当前温度是目标值还是低于或高于该值。版权所有（C）2010，JPO＆INPIT

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