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    • 4. 发明申请
    • COMPUTER-AIDED DISPATCH INCLUDING AUTOMATIC DIVERSIONS
    • 计算机辅助调度,包括自动分流
    • WO2018052670A1
    • 2018-03-22
    • PCT/US2017/047976
    • 2017-08-22
    • INTERGRAPH CORPORATION
    • KYEMBA, Heather RuthCOOLEY, Joshua Bret
    • G06Q10/06G06Q50/22G06Q50/30G06Q10/08G06Q10/04
    • Embodiments of the present invention disclose a computer-implemented methodology for automatically indicating in a computer-aided dispatch system for a plurality of assignable participants, such as emergency vehicles, to be dispatched to one of a plurality of facilities, whether a facility is in a diverting status or a receiving status. A centralized database receives a change in status for a vehicle for use in determining the status of a facility. In response to receiving the change in status for the vehicle, the status information about the vehicle including a current status and a prior status is transmitted to one or more client programs. A client program receives the current status and the prior status of the vehicle and uses the current status and prior status of the vehicle along with a criteria set to determine if any of the plurality of facilities' status should be changed from receiving to diverting or from diverting to receiving.
    • 本发明的实施例公开了一种计算机实现的方法,用于在计算机辅助调度系统中自动指示多个可分配参与者(例如紧急车辆)被分派到多个可分配参与者 设施,设施是否处于转移状态或接收状态。 集中式数据库接收车辆的状态变化以用于确定设施的状态。 响应于接收到车​​辆的状态改变,将包括当前状态和先前状态的关于车辆的状态信息发送到一个或多个客户端程序。 客户程序接收车辆的当前状态和先前状态并且使用车辆的当前状态和先前状态以及标准集合来确定多个设施的状态中的任何状态是否应该从接收改变为改变或从 转移到接收。
    • 6. 发明申请
    • HIGH-AVAILABILITY SUPER SERVER
    • 高可用性超级服务器
    • WO1997030399A1
    • 1997-08-21
    • PCT/US1997002571
    • 1997-02-19
    • INTERGRAPH CORPORATION
    • INTERGRAPH CORPORATIONMcKINNEY, Arthur, C.McCARVER, Charles, H., Jr.SAMIEE, Vahid
    • G06F15/16
    • G06F12/0813G06F12/0822G06F12/0831G06F13/4022G06F13/4077G06F15/173H03K19/00361H03K19/018521
    • The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors. The present invention comprises a plurality of processor segments (a cluster of one or more CPU's) memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel. The processors, in preferred embodiment, may further include an internal cache and flags associated with the cache to allow multi-processor cache coherency in external write-back cache.
    • 本发明提供了一种具有分段存储架构的多处理器计算机的高可用性并行处理服务器。 处理器被分组为处理器集群,在优选实施例中,每个集群由多达四个处理器组成。 每个处理器集群具有用于与每个存储器段通信的专用存储器总线。 本发明被设计为能够在优选实施例中保持所有处理器和存储器段之间的相干交互。 优选实施例使用Intel Pentium-Pro处理器。 本发明包括多个处理器段(一个或多个CPU的集群)存储器段(存储器的独立区域)和存储器通信总线(与存储器段通信的路径)。 每个处理器段具有用于与每个存储器段进行交互的专用通信总线,允许不同处理器并行工作时并行访问不同的存储器段。 在优选实施例中,处理器还可以包括与高速缓存相关联的内部高速缓存和标志,以允许外部回写高速缓存中的多处理器高速缓存一致性。