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1. 发明专利

DE3940302C2 未知
公开(公告)号：DE3940302C2
公开(公告)日：1993-02-25
申请号：DE3940302
申请日：1989-12-06
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： BUSH, GREGORY FREDERICK, ENDICOTT, N.Y., US , KEENER, DON STEVEN , MOREL, JEANNE ELLEN , VOORHEES, RICHARD, W., BOCA RATON, FL., US
IPC分类号： G06F12/06
摘要： In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

2. 发明专利

DE2523221C2 未知
公开(公告)号：DE2523221C2
公开(公告)日：1992-09-17
申请号：DE2523221
申请日：1975-05-26
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： CASS, EUGENE EDWARD, JUNCTION, N.Y., US
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/118

3. 发明专利

DE3914265C2 未知
公开(公告)号：DE3914265C2
公开(公告)日：1992-01-09
申请号：DE3914265
申请日：1989-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： BEGUN, RALPH MURRAY, BOCA RATON, FLA., US , BLAND, PATRICK MAURICE , DEAN, MARK EDWARD, DELRAY BEACH, FLA., US
IPC分类号： G06F9/38 , G06F12/08
摘要： In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

4. 发明专利

DE4018481C2 未知
公开(公告)号：DE4018481C2
公开(公告)日：1991-08-08
申请号：DE4018481
申请日：1990-06-09
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： BEGUN, RALPH MURRAY, BOCA RATON, FLA., US , BLAND, PATRICK MAURICE , DEAN, MARK EDWARD, DELRAY BEACH, FLA., US
IPC分类号： G06F13/36 , G06F13/28 , G06F13/362
摘要： A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

5. 发明专利

DE3810232C2 未知
公开(公告)号：DE3810232C2
公开(公告)日：1991-01-31
申请号：DE3810232
申请日：1988-03-25
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： TRYNOSKY, STEPHEN WAYNE, BOCA RATON, FL., US , PARSONS, JR., DONALD HOLCOMBE, PALM BEACH, FL., US
IPC分类号： G06F3/153 , G09G1/00 , G09G1/16 , G09G5/22 , G09G5/24
摘要： A raster scan display system uses a RAM character generator and a dual port video buffer random access memory. The dual port buffer has a shift register output for holding a row of data from the random access memory. The buffer has two partitions, one containing, at consecutive locations, character data and attribute data, the other, character data and font data. In a first mode of operation using the first partition, data transferred to the shift register comprises character data to address the character generator store and attribute data for combination with font data retrieved from the character generator store to provide video data. In a second mode, using the second partition, character and font data transferred to the shift register is used to address and update the character generator store.

6. 发明专利

DE3909909C2 未知
公开(公告)号：DE3909909C2
公开(公告)日：1990-05-31
申请号：DE3909909
申请日：1989-03-25
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： BEGUN, RALPH MURRAY, BOCA RATON, FLA., US , BLAND, PATRICK MAURICE, DELRAY BEACH, FLA., US , DEAN, MARK EDWARD, DELRAY BEACH, FLA., US
IPC分类号： G06F12/08
摘要： A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

7. 发明专利

DE3809831C2 未知
公开(公告)号：DE3809831C2
公开(公告)日：1989-09-07
申请号：DE3809831
申请日：1988-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： HEATH, CHESTER ASBURY, BOCA RATON, FLA., US , JACKSON, KEVIN MICHAEL, DELRAY BEACH, FLA., US , JUDICE, DARRYL EDMOND, BOYNTON BEACH, FLA., US , PESTONJI, HOSHANG RATAN, CORAL SPRINGS, FLA., US
IPC分类号： G06F9/48 , G06F9/46 , G06F13/24 , G06F15/78
摘要： A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.

8. 发明专利

DE2746700C2 未知
公开(公告)号：DE2746700C2
公开(公告)日：1988-12-22
申请号：DE2746700
申请日：1977-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： AYERS, ROBERT LEE, MANASSAS, VA., US , HAMAKER, RAYMOND WEAVER, CATHARPIN, VA., US
IPC分类号： H01L21/761 , H01L29/06 , H01L21/76 , H01L27/04
摘要： A structure of a semiconductor device for preventing the degradation of the epitactic isolation joint subjected to direct polarization, comprising: an epitactic layer of silicon of a first type of conductivity; at least one region of isolation of a second type of conductivity formed in the substrate; a safety ring of said second type of conductivity formed around the isolation region to prevent the diffusion of ionic contaminants from the isolation region when the isolation region is subjected to direct polarization with respect to said epitactic layer. (Machine-translation by Google Translate, not legally binding)

9. 发明专利

DE2158683C3 未知
公开(公告)号：DE2158683C3
公开(公告)日：1988-09-29
申请号：DE2158683
申请日：1971-11-26
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： CLOSS, FELIX HUGO , MUELLER, HANS RUDOLF , WILD, DANIEL, ADLISWIL, CH
IPC分类号： H04J3/06 , H04J3/24 , H04Q11/04 , H04L11/00
摘要： A decentralized time division multiplex communication system having independent exchange modules arranged to individually set up connections without the need of central control. Commonality of hardware is limited to a simple interconnection unit, and a clock allowing synchronization of all modules. Each exchange module, with its associated group of terminals, is arranged to form a time division multiplex system of first order. The exchange modules, together with the interconnection unit, are arranged to form a super-multiplex system, i.e., a time division multiplex system of second order. All bus line time division multiplex channels of all exchange modules are interspersed on the interconnection unit. To each of these bus line channels, a time slot is permanently assigned in the super-multiplex time frame.

10. 发明专利

DE2840243C2 未知
公开(公告)号：DE2840243C2
公开(公告)日：1988-05-26
申请号：DE2840243
申请日：1978-09-15
申请人： INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US
发明人： KASSON, JAMES M., SANTA CLARA, CALIF., US , GRAHAM, MARTIN H., BERKELEY, CALIF., US
IPC分类号： H04L1/00 , H03M1/00 , H03M1/08 , H04B14/04 , H04B15/00 , H03M1/20
摘要： In a digital information transmission system having an analog-to-digital converter (ADC), an information transmission medium, and a digital-to-analog converter (DAC) all located between a transmitting station and a receiving station, signal transmission is improved by injection of a controlled signal in the form of a symmetric triangle wave sweep having a maximum peak-to-peak amplitude exceeding the magnitude of a few quantization intervals of the ADC and the DAC, introducing frequency components concentrated outside the system frequency spectrum. A class of controlled signals is disclosed. In the preferred embodiment, the controlled signal is injected into the analog information input signal prior to conversion to digital form. The injected signal predominates whenever the amplitude of spurious noise signals is less than the amplitude of the injected signal and the level of the input of the ADC is near a quantizing interval transition point so that subsequent analog output signals from the DAC have frequencies concentrated outside the frequency spectrum of the system. The DAC output signals are subsequently filtered by a post-sampling filter having a pass-band characteristic coextensive with the system frequency spectrum so that the injected signal components are removed before coupling to the signal output utilization device. Alternatively, a digital representation of the controlled signal may be added to the information signal after conversion to digital form and subsequently filtered from the information signal.

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