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1. 发明专利

TWI679751B 半導體存儲設備及其製造方法及包括存儲設備的電子設備有权
简体标题：半导体存储设备及其制造方法及包括存储设备的电子设备
公开(公告)号：TWI679751B
公开(公告)日：2019-12-11
申请号：TW107144668
申请日：2018-12-12
申请人：中國科學院微電子研究所 , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人：朱慧瓏 , ZHU, HUILONG
IPC分类号： H01L27/105 , G11C11/22

2. 发明专利

TW201921648A 半導體存儲設備及其製造方法及包括存儲設備的電子設備审中-公开
简体标题：半导体存储设备及其制造方法及包括存储设备的电子设备
公开(公告)号：TW201921648A
公开(公告)日：2019-06-01
申请号：TW107144668
申请日：2018-12-12
申请人：中國科學院微電子研究所 , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人：朱慧瓏 , ZHU, HUILONG
IPC分类号： H01L27/105 , G11C11/22
摘要：本發明揭露一種半導體存儲設備及其製造方法及包括該存儲設備的電子設備。根據實施例，半導體存儲設備可以包括：襯底；設置在襯底上的存儲單元陣列，所述存儲單元陣列中的存儲單元按行和列排列，各存儲單元包括豎直延伸的柱狀有源區，柱狀有源區包括分別位於上下兩端的源/汲區以及位於源/汲區之間的溝道區；以及在襯底上形成的多條位線，各條位線分別位於相應存儲單元列的下方，且與相應列中各存儲單元下端的源/汲區電連接，其中，各存儲單元還包括繞溝道區外周形成的閘堆疊，相應存儲單元行中各存儲單元的閘堆疊中的閘導體層沿著行的方向彼此連續地延伸從而構成相應的字線。
简体摘要：本发明揭露一种半导体存储设备及其制造方法及包括该存储设备的电子设备。根据实施例，半导体存储设备可以包括：衬底；设置在衬底上的存储单元数组，所述存储单元数组中的存储单元按行和列排列，各存储单元包括竖直延伸的柱状有源区，柱状有源区包括分别位于上下两端的源/汲区以及位于源/汲区之间的沟道区；以及在衬底上形成的多条位线，各条位线分别位于相应存储单元列的下方，且与相应列中各存储单元下端的源/汲区电连接，其中，各存储单元还包括绕沟道区外周形成的闸堆栈，相应存储单元行中各存储单元的闸堆栈中的闸导体层沿着行的方向彼此连续地延伸从而构成相应的字线。

3. 发明专利

TW201836112A 互連結構及其製造方法、包括互連結構的電子設備审中-公开
简体标题：互链接构及其制造方法、包括互链接构的电子设备
公开(公告)号：TW201836112A
公开(公告)日：2018-10-01
申请号：TW107122079
申请日：2018-06-27
申请人：中國科學院微電子研究所 , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人：朱慧瓏 , ZHU, HUILONG
IPC分类号： H01L23/535 , H01L21/768
摘要：本發明揭露一種互連結構及其製造方法以及包括這種互連結構的電子設備。根據實施例，互連結構可以包括：處於第一高度的第一互連線，至少包括沿第一方向延伸的第一部分；處於比第一高度高的第二高度的第二互連線，至少包括沿與第一方向交叉的第二方向延伸的第二部分；設於第一互連線的第一部分與第二互連線的第二部分之間用於將第一互連線和第二互連線電連接的過孔插塞，其中，過孔插塞包括分別與第一部分的相對側壁實質上平行延伸的第一對側壁以及分別與第二部分的相對側壁實質上平行延伸的第二對側壁。
简体摘要：本发明揭露一种互链接构及其制造方法以及包括这种互链接构的电子设备。根据实施例，互链接构可以包括：处于第一高度的第一互连接，至少包括沿第一方向延伸的第一部分；处于比第一高度高的第二高度的第二互连接，至少包括沿与第一方向交叉的第二方向延伸的第二部分；设于第一互连接的第一部分与第二互连接的第二部分之间用于将第一互连接和第二互连接电连接的过孔插塞，其中，过孔插塞包括分别与第一部分的相对侧壁实质上平行延伸的第一对侧壁以及分别与第二部分的相对侧壁实质上平行延伸的第二对侧壁。

4. 发明专利

SG11202012334SA METHOD FOR MANUFACTURING SILICON OPTICAL INTERPOSER, METHOD FOR MANUFACTURING THREE-DIMENSIONAL STRUCTURE, METHOD FOR INTEGRATING SURFACE-ELECTRODE ION TRAP AND SILICON PHOTOELECTRONIC DEVICE, INTEGRATED STRUCTURE, AND THREE-DIMENSIONAL STRUCTURE 未知
公开(公告)号：SG11202012334SA
公开(公告)日：2021-06-29
申请号：SG11202012334S
申请日：2019-11-21
申请人： INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES
发明人： YANG YAN , LI ZHIHUA , WANG WENWU
IPC分类号： H01L31/0203
摘要： An integrated method for a silicon optical adapter adapter plate and a three-dimensional architecture, capable of making the chip encapsulation area smaller, and achieving a higher integration level, a smaller electrical signal delay and a higher bandwidth and speed, and an integrated method for a surface electrode ion trap, a silicon optical device and a three-dimensional architecture, an integrated structure and a three-dimensional architecture with a strong stability, miniaturization, versatility and expandability. The integration of the three-dimensional architecture is realized on the basis of the integration of a through-silicon via and a silicon optical device, so that the integrated chip area can be smaller and the integration level can be higher, and the formed three-dimensional architecture has a smaller electrical signal delay and a higher bandwidth and speed. The surface electrode ion trap is integrated with a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, a silicon grating and/or a silicon nitride grating and a through-silicon via. After being powered on, the surface electrode ion trap is used to capture ions and trap same in a certain range. A laser source is coupled to the silicon grating and/or the silicon nitride grating by using any coupling mode such as end-face coupling. The laser is emitted to the ions via the silicon grating and/or the silicon nitride grating on three orientations to complete addressing. The ions can undergo energy level transition after being excited by light. After energy level transition, the ions can radiate fluorescent light. The fluorescent light is detected by the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the detection of quantum bit information is finally completed.

5. 发明公开

EP3093874A1 TUNGSTEN LAYER DEPOSITING METHOD CAPABLE OF IMPROVING ADHESIVE PERFORMANCE AND FILLING PERFORMANCE 有权
标题翻译： WOLFRAMSCHICHTABLAGERUNGSVERFAHREN ZUR VERBESSERUNG DER KLEBSTOFF- UNDFÜLLIST
公开(公告)号：EP3093874A1
公开(公告)日：2016-11-16
申请号：EP14868723.9
申请日：2014-02-20
申请人： Institute Of Microelectronics, Chinese Academy Of Sciences
发明人： XU, Qiang , ZHAO, Chao , LUO, Jun , WANG, Guilei , YANG, Tao , LI, Junfeng
IPC分类号： H01L21/285 , C23C16/08 , C23C16/52
CPC分类号： H01L21/28562 , C23C16/0272 , C23C16/14 , C23C16/45525 , H01L21/28079 , H01L21/28088 , H01L21/32051 , H01L21/76876 , H01L21/76877 , H01L29/66545
摘要： A method of depositing a Tungsten (W) layer is provided. The method may include pre-processing a substrate by depositing a SiH 4 base W film on a surface of the substrate, and depositing a B 2 H 6 base W layer on the pro-processed surface. By such a method, it is possible not only to achieve an excellent filling behavior, but also to improve adhesion.
摘要翻译：提供了沉积钨（W）层的方法。该方法可以包括通过在衬底的表面上沉积SiH 4基底W膜并在预处理表面上沉积B 2 H 6基底W层来预处理衬底。通过这种方法，不仅可以实现优异的填充性能，而且可以提高粘合性。

6. 发明授权

EP3093874B1 TUNGSTEN LAYER DEPOSITING METHOD CAPABLE OF IMPROVING ADHESIVE PERFORMANCE AND FILLING PERFORMANCE 有权
公开(公告)号：EP3093874B1
公开(公告)日：2019-04-03
申请号：EP14868723.9
申请日：2014-02-20
申请人： Institute Of Microelectronics, Chinese Academy Of Sciences
发明人： XU, Qiang , ZHAO, Chao , LUO, Jun , WANG, Guilei , YANG, Tao , LI, Junfeng
IPC分类号： C23C16/08 , C23C16/52 , H01L21/28 , H01L21/3205 , H01L21/285 , H01L21/768 , H01L29/66

7. 发明公开

EP2930739A1 SUPER-JUNCTION MANUFACTURING METHOD 有权
标题翻译： HERSTELLUNGSVERFAHRENFÜRSUPERVERBINDUNGEN
公开(公告)号：EP2930739A1
公开(公告)日：2015-10-14
申请号：EP12889660.2
申请日：2012-12-06
申请人： Institute Of Microelectronics, Chinese Academy Of Sciences , Jiangsu Cas-IGBT Technology Co., Ltd , Jiangsu R&D Center For Internet Of Things
发明人： ZHANG, Wenliang , ZHU, Yangjun , LU, Shuojin , TIAN, Xiaoli , CHU, Weili
IPC分类号： H01L21/00 , H01L21/336 , H01L21/261 , H01L21/263
CPC分类号： H01L21/261 , H01L21/263 , H01L29/0634 , H01L29/7395 , H01L29/7802
摘要： Provided is a super-junction manufacturing method, comprising: providing a lightly doped substrate (S11); employing a transmutation doping process to form a P-type heavily doped region (S12) or an N-type heavily doped region (S13); and performing annealing treatment (S14); or providing a first-type heavily doped substrate; employing the transmutation doping process to form a second-type heavily doped region; and performing annealing treatment. Thereby, the manufacturing process is simplified, and production costs are reduced.
摘要翻译：提供一种超接合制造方法，包括：提供轻掺杂衬底（S11）; 采用变形掺杂工艺以形成P型重掺杂区域（S12）或N型重掺杂区域（S13）; 并进行退火处理（S14）。或提供第一种重掺杂衬底; 采用转化掺杂工艺形成第二种重掺杂区; 并进行退火处理。由此，简化了制造工序，降低了生产成本。

8. 发明公开

EP2562794A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP2562794A1
公开(公告)日：2013-02-27
申请号：EP10850023.2
申请日：2010-09-17
申请人： Institute Of Microelectronics, Chinese Academy Of Sciences
发明人： YIN, Haizhou , LUO, Zhijiong , ZHU, Huilong
IPC分类号： H01L21/28 , H01L29/41
CPC分类号： H01L23/485 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device and a method for fabricating the same. The semiconductor device comprises: a semiconductor substrate; gates, spacers on both sides of the respective gates, and source/drain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source/drain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source/drain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source/drain regions, and the lower contacts, wherein the respective source/drain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Embodiments of the present invention apply to the fabrication of contacts for semiconductor devices.
摘要翻译：提供了一种半导体器件及其制造方法。该半导体器件包括：半导体衬底; 栅极，位于各个栅极两侧的隔离物，以及形成在半导体衬底上的各个隔离物两侧的源极/漏极区; 位于各个源极/漏极区域上且邻接所述间隔件的外侧壁的下触点，其底部覆盖各个源极/漏极区域的至少一部分; 在所述栅极，所述隔离物，所述源极/漏极区和所述下部触点上形成的层间电介质层，其中所述晶体管结构中的每一个的各个源极/漏极区通过所述层间电介质层 ; 以及形成在层间电介质层中并且对应于下触点的上触点。本发明的实施例适用于制造用于半导体器件的触点。

9. 发明公开

US20240379794A1 3DS FET AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20240379794A1
公开(公告)日：2024-11-14
申请号：US18462613
申请日：2023-09-07
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huaxiang YIN , Peng ZHAO , Zhenhua WU , Jiaxin YAO
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.

10. 发明公开

US20240371637A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240371637A1
公开(公告)日：2024-11-07
申请号：US18624334
申请日：2024-04-02
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong ZHU , Zhuo CHEN , Jinbiao LIU , Junfeng LI , Jun LUO
IPC分类号： H01L21/02 , H01L21/8234 , H01L27/088
CPC分类号： H01L21/02675 , H01L21/823412 , H01L21/823418 , H01L27/088
摘要： A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

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