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1. 发明申请

WO2008057371A2 TRAP-CHARGE NON-VOLATILE SWITCH CONNECTOR FOR PROGRAMMABLE LOGIC 审中-公开
标题翻译：用于可编程逻辑的TRAP-CHARGE非易失性开关连接器
公开(公告)号：WO2008057371A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/023050
申请日：2007-11-01
申请人： GUMBO LOGIC, INC , OGURA, Tomoko , OGURA, Seiki , OGURA, Nori
发明人： OGURA, Tomoko , OGURA, Seiki , OGURA, Nori
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择用于可编程逻辑应用（例如FPGA）中的逻辑互连晶体管。非易失性俘获电荷元件是位于半导体衬底表面上的控制栅下方和氧化物上方的绝缘体。优选实施例是一种集成器件，包括夹在两个非易失性阱电荷存储部分之间的字门部分，其中集成器件连接在高偏压，低偏压和输出之间。输出由连接到字门部分正下方的通道的扩散形成。两个存储部分的编程状态确定高偏置或低偏置是否耦合到连接到输出扩散的逻辑互连晶体管。

2. 发明申请

WO2008057371A3 TRAP-CHARGE NON-VOLATILE SWITCH CONNECTOR FOR PROGRAMMABLE LOGIC 审中-公开
标题翻译：用于可编程逻辑的TRAP充电非易失性开关连接器
公开(公告)号：WO2008057371A3
公开(公告)日：2008-10-23
申请号：PCT/US2007023050
申请日：2007-11-01
申请人： GUMBO LOGIC INC , OGURA TOMOKO , OGURA SEIKI , OGURA NORI
发明人： OGURA TOMOKO , OGURA SEIKI , OGURA NORI
IPC分类号： G06F13/00
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

3. 发明申请

WO2009102458A1 HIGH DENSITY VERTICAL STRUCTURE NITRIDE FLASH MEMORY 审中-公开
标题翻译：高密度垂直结构氮化物闪存
公开(公告)号：WO2009102458A1
公开(公告)日：2009-08-20
申请号：PCT/US2009/000905
申请日：2009-02-12
申请人： GUMBO LOGIC, INC. , OGURA, Seiki , IWASAKI, Tomoko, Ogura , OGURA, Nori
发明人： OGURA, Seiki , IWASAKI, Tomoko, Ogura , OGURA, Nori
IPC分类号： H01L21/8247
CPC分类号： H01L27/10876 , G11C16/10 , H01L21/28282 , H01L27/108 , H01L27/10879 , H01L27/11563 , H01L27/11565 , H01L27/11568 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non- volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
摘要翻译：描述具有具有垂直和可能水平分量的存储器通道的存储器的电荷陷阱型。本发明包括用于高速和高可靠性非易失性存储器以及高密度非易失性存储器的同时空穴和电子注入操作的新操作方法。还描述了用于高密度存储器阵列和高速存储器阵列的阵列实现及其制造方法。

4. 发明公开

EP2084613A2 TRAP-CHARGE NON-VOLATILE SWITCH CONNECTOR FOR PROGRAMMABLE LOGIC 审中-公开
标题翻译：用于可编程逻辑的TRAP-CHARGE非易失性开关连接器
公开(公告)号：EP2084613A2
公开(公告)日：2009-08-05
申请号：EP07839887.2
申请日：2007-11-01
申请人： Gumbo Logic, Inc.
发明人： OGURA, Tomoko , OGURA, Seiki , OGURA, Nori
IPC分类号： G06F13/00
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择可编程逻辑应用（例如FPGA）中使用的逻辑互连晶体管。非易失性俘获电荷元件是位于半导体衬底表面上的控制栅下方和氧化物上方的绝缘体。优选实施例是一种集成器件，包括夹在两个非易失性阱电荷存储部分之间的字门部分，其中集成器件连接在高偏压，低偏压和输出之间。输出由连接到字门部分正下方的通道的扩散形成。两个存储部分的编程状态确定高偏置或低偏置是否耦合到连接到输出扩散的逻辑互连晶体管。

5. 发明公开

EP2084613A4 TRAP-CHARGE NON-VOLATILE SWITCH CONNECTOR FOR PROGRAMMABLE LOGIC 审中-公开
标题翻译：不挥发FALL-充电开关连接器可编程逻辑
公开(公告)号：EP2084613A4
公开(公告)日：2009-10-21
申请号：EP07839887
申请日：2007-11-01
申请人： GUMBO LOGIC INC
发明人： OGURA TOMOKO , OGURA SEIKI , OGURA NORI
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115

6. 发明授权

US07742336B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US07742336B2
公开(公告)日：2010-06-22
申请号：US11982172
申请日：2007-11-01
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

7. 发明申请

US20090200603A1 High density vertical structure nitride flash memory 有权
标题翻译：高密度垂直结构氮化物闪存
公开(公告)号：US20090200603A1
公开(公告)日：2009-08-13
申请号：US12378108
申请日：2009-02-11
申请人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , G11C16/10 , H01L21/28282 , H01L27/108 , H01L27/10879 , H01L27/11563 , H01L27/11565 , H01L27/11568 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
摘要翻译：描述具有具有垂直和可能水平分量的存储器通道的存储器的电荷陷阱型。本发明包括用于高速和高可靠性非易失性存储器以及高密度非易失性存储器的同时空穴和电子注入操作的新操作方法。还描述了用于高密度存储器阵列和高速存储器阵列的阵列实现及其制造方法。

8. 发明申请

US20100259986A1 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US20100259986A1
公开(公告)日：2010-10-14
申请号：US12802910
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

9. 发明申请

US20100259981A1 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US20100259981A1
公开(公告)日：2010-10-14
申请号：US12802888
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

10. 发明申请

US20100261324A1 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US20100261324A1
公开(公告)日：2010-10-14
申请号：US12802894
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： H01L21/336
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

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