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1. 发明专利

JP2009278103A Semiconductor package featuring flip-chip die sandwiched between metal layers 审中-公开
标题翻译：金属层之间的半导体封装特征片状芯片
公开(公告)号：JP2009278103A
公开(公告)日：2009-11-26
申请号：JP2009116937
申请日：2009-05-13
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： TSUI ANTHONY C , ESLAMY MOHAMMAD
IPC分类号： H01L23/40 , H01L23/29 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49816 , H01L21/56 , H01L23/4334 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/072 , H01L25/074 , H01L2224/0401 , H01L2224/0603 , H01L2224/16145 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/371 , H01L2224/40245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a flip-chip package for semiconductor devices, which has good thermal conductivity and can be manufactured at a low cost and features a die sandwiched between metal layers. SOLUTION: One metal layer 224 comprises portions of a lead frame configured to be in electrical and thermal communication with various pads on a first surface of a die 202 (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer 226 is configured to be in at least thermal communication with the opposite side of the die 202. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有良好导热性并且可以以低成本制造的半导体器件的倒装芯片封装，并且具有夹在金属层之间的管芯。解决方案：一个金属层224包括引线框架的部分，其被配置为通过焊球触点与芯片202的第一表面（例如，IC焊盘或MOSFET栅极或源极焊盘）上的各种焊盘电连接和热连通。另一金属层226被配置为与模具202的相对侧至少热连通。版权所有：（C）2010，JPO＆INPIT

2. 发明专利

JP2008124410A Package design for vertical conduction dies 审中-公开
标题翻译：用于垂直导管的包装设计
公开(公告)号：JP2008124410A
公开(公告)日：2008-05-29
申请号：JP2006353894
申请日：2006-12-28
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： HARNDEN JAMES , CHIA ANTHONY , WONG LIMING , YANG HONGBO
IPC分类号： H01L21/60
CPC分类号： H01L23/49541 , H01L23/4952 , H01L23/49524 , H01L23/49575 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/91 , H01L2224/05554 , H01L2224/40091 , H01L2224/40245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/4847 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/73221 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/2076 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2924/01006 , H01L2224/37099
摘要： PROBLEM TO BE SOLVED: To cope with the necessity for an improved technology of manufacturing packages for a vertical conduction discrete device and other dies requiring that contact resistance is low on both sides in this technology field. SOLUTION: An embodiment according to the present invention is related to packaging design for a vertical conduction semiconductor device including contacts having low electric resistance with the surface of the top part of a die. In one embodiment, this low-resistance contact is employed by using an aluminum ribbon for bonding with one side part or both side parts of a lead frame. According to a specific mode, the vertical conduction device may be built in a Quad Flat No-lead (QFN) package that is improved for this purpose. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决在该技术领域中需要在两侧上要求接触电阻低的垂直传导分立装置和其它模具的制造包装的改进技术的必要性。解决方案：根据本发明的实施例涉及用于垂直传导半导体器件的封装设计，其包括具有与管芯顶部表面的低电阻的触点。在一个实施例中，通过使用用于与引线框架的一个侧面部分或两个侧面部分结合的铝带来采用该低电阻接触。根据具体的模式，垂直传导装置可以内置在四平面无引线（QFN）封装中，该封装改进了该目的。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2009267398A Semiconductor device package having shape formed using stamping processing 审中-公开
标题翻译：具有使用冲压加工形成的形状的半导体器件封装
公开(公告)号：JP2009267398A
公开(公告)日：2009-11-12
申请号：JP2009091309
申请日：2009-04-03
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： TSUI ANTHONY C , ESLAMY MOHAMMAD , CHIA ANTHONY , YANG HONGBO , MING ZHOU , XU JIAN
IPC分类号： H01L23/50 , H01L23/12
CPC分类号： H01L23/49575 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49551 , H01L23/49582 , H01L23/49586 , H01L24/27 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/27013 , H01L2224/2919 , H01L2224/32013 , H01L2224/32245 , H01L2224/40245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/48599 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48699 , H01L2224/48739 , H01L2224/48744 , H01L2224/48755 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/83051 , H01L2224/83191 , H01L2224/83192 , H01L2224/83801 , H01L2224/8385 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , Y10T29/49124 , H01L2924/00012 , H01L2924/00 , H01L2224/37099
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a lead frame which does not require partial etching. SOLUTION: Portions of the lead frame, such as pins 208, are extruded by stamping processing from a horizontal plane of a die pad 204. The stamping processing can impart indentations 204a, 208a or a complex cross-sectional profile, such as chamfered profile, to portions of one or both of the pins 208 and the die pad 204. Complexity provided by such a stamped cross-sectional profile serves to enhance the mechanical interlocking of the lead frame within the plastic molding of the package body. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造不需要局部蚀刻的引线框架的方法。引线框架（例如引脚208）的部分通过冲压加工从管芯焊盘204的水平面挤出。冲压加工可以赋予凹口204a，208a或复杂的横截面轮廓，例如倒角轮廓到销208和芯片垫204中的一个或两个的部分。由这种冲压的横截面轮廓提供的复杂性用于增强引线框架在封装主体的塑料模制件内的机械互锁。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009131144A Bidirectional reverse blocking battery switch 有权
标题翻译：双向反向阻塞电池开关
公开(公告)号：JP2009131144A
公开(公告)日：2009-06-11
申请号：JP2008023416
申请日：2008-02-04
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： HARNDEN JAMES , CHIA ANTHONY , WONG LIMING , YANG HONGBO , TSUI ANTHONY C , HUI TENG , ZHOU MIN
IPC分类号： H02J7/00 , H01M10/44
CPC分类号： H01M10/44 , H01L2224/48091 , H01L2224/48247 , H01L2924/13091 , H01L2924/3011 , H02J7/0031 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a bidirectional reverse blocking battery switch.
SOLUTION: An aspect of the invention is an improved die layout for the bidirectional reverse blocking battery switch. In one aspect, two switches do not contact each other at their ends, but are oriented so as to be juxtaposed within a die package. The constitution reduces the total switch resistance with regard to a given die area; in many cases, the resistance is fully reduced so as to avoid a usage of a back metal for conforming to a resistance standard. The back metal is eliminated so as to reduce the total cost of the die package and eliminate potential failure mode, due to manufacturing of the back metal. In some other aspects of the invention, increase in pin connections and a pin pitch can be allowed. Redundant connections for large current connections are formed. The electrical resistance and the thermal resistance are reduced, and as a result, the cost for manufacturing or implementing the die package is minimized.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供双向反向阻断电池开关。解决方案：本发明的一个方面是用于双向反向阻断电池开关的改进的管芯布局。在一个方面，两个开关在它们的端部处不彼此接触，而是被定向成在管芯封装内并置。该结构相对于给定的模具面积降低总开关电阻; 在许多情况下，电阻被完全降低，以避免使用背面金属以符合电阻标准。由于背金属的制造，背面金属被去除以便降低模具封装的总成本并消除潜在的故障模式。在本发明的一些其他方面，可以允许引脚连接的增加和引脚间距。形成大电流连接的冗余连接。降低了电阻和耐热性，结果，制造或实施模具封装的成本最小化。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008147604A Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls 审中-公开
标题翻译：半导体器件封装特征与投影爆破或爆炸的封装铅笔
公开(公告)号：JP2008147604A
公开(公告)日：2008-06-26
申请号：JP2007009845
申请日：2007-01-19
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： HARNDEN JAMES , WILLIAMS RICHARD K , CHIA ANTHONY , HUI TENG , YANG HONGBO , MING ZHOU , TSUI ANTHONY C
IPC分类号： H01L23/50 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49503 , H01L23/49524 , H01L23/49562 , H01L23/49572 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16245 , H01L2224/37124 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/10161 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/0401 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device package featuring an encapsulated leadframe with projecting bumps or balls. SOLUTION: The semiconductor device package 200 features a leadframe in electrical communication with a supported die 202 through electrically conductive bumps or balls 206. By precluding the need for a separate die pad and horizontal isolation between an edge of the die pad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump-on-leadframe processes allow an increase in a space available to the die for a package footprint and also allow multiple dice and/or multiple passive devices to occupy the space in the package which has conventionally been occupied by a die pad. The result enables combination of dice and technologies required for complete subsystems in a conventional small footprint specified by JEDEC. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有突出凸起或球的封装引线框的半导体器件封装。解决方案：半导体器件封装200具有通过导电凸块或球206与支撑的裸片202电连通的引线框架。通过排除对单独管芯焊盘的需要和在芯片焊盘的边缘与相邻的焊盘之间的水平隔离非整体引线或引脚，通过引脚框架过程制造的封装的实施例允许增加用于封装封装的管芯可用空间，并且还允许多个管芯和/或多个无源器件占据封装中的空间其通常被芯片垫占据。该结果使得JEDEC规定的常规小尺寸中的完整子系统所需的骰子和技术的组合。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007300088A Semiconductor device package lead frame formed with a plurality of metal layers 审中-公开
标题翻译：半导体器件包装与多层金属层形成的引线框架
公开(公告)号：JP2007300088A
公开(公告)日：2007-11-15
申请号：JP2007104458
申请日：2007-04-12
申请人： Gem Services Inc , ジーイーエムサービシズインコーポレーティッド
发明人： HARNDEN JAMES , CHIA ANTHONY , WONG LIMING , YANG HONGBO
IPC分类号： H01L23/50
CPC分类号： H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device package lead frame formed with a plurality of metal layers.
SOLUTION: The lead frame with a raised shape for using a semiconductor package is made by bonding at least two metal layers 450, 452. A first metal layer 450 demarcates a dimension in the lateral direction of the lead frame containing an arbitrary die pad and a lead. A second metal layer 452 bonded to the first metal layer demarcates a raised shape in the lead frame, for example a step for physically securing the lead frame on the package body. A plurality of the metal layers can be bonded by a number of available technologies including ultrasonic welding, soft soldering, or use of epoxy resins. After or before bonding, a further shape such as an offset or a groove can be formed by coining or stamping one or a plurality of metal layers.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成有多个金属层的半导体器件封装引线框架。解决方案：使用半导体封装的凸起形状的引线框架通过键合至少两个金属层450,452而形成。第一金属层450划分包含任意裸片的引线框架的横向方向上的尺寸垫和铅。结合到第一金属层的第二金属层452划分引线框架中的凸起形状，例如用于将引线框架物理地固定在封装主体上的步骤。多个金属层可以通过包括超声波焊接，软焊接或环氧树脂的使用在内的许多可用技术来结合。在接合之后或之前，可以通过压印或冲压一个或多个金属层来形成诸如偏移或凹槽的另外的形状。版权所有（C）2008，JPO＆INPIT

7. 发明申请

WO2005112102A2 CHEMICAL-ENHANCED PACKAGE SINGULATION PROCESS 审中-公开
标题翻译：化学增强包装整理工艺
公开(公告)号：WO2005112102A2
公开(公告)日：2005-11-24
申请号：PCT/US2005016482
申请日：2005-05-10
申请人： GEM SERVICES INC , YILMAZ HAMZA , CHIA ANTHONY , ZENG XIAOGUANG , WONG HIE MING , WANG LIMING , ZHANG YIJU
发明人： YILMAZ HAMZA , CHIA ANTHONY , ZENG XIAOGUANG , WONG HIE MING , WANG LIMING , ZHANG YIJU
IPC分类号： H01L21/44 , H01L21/68 , H01L23/31 , H01L23/495
CPC分类号： H01L23/49548 , H01L21/6835 , H01L23/3107 , H01L24/48 , H01L24/97 , H01L2221/68331 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Singulation of individual electronic packages fabricated as part of a common matrix, is accomplished by mask patterning and chemical exposure in combination with physical sawing. In one embodiment of a singulation process in accordance with the present invention, an initial, shallow saw cut into inter-package regions of the matrix exposes underlying metal to subsequent chemical etching steps. In an alternative embodiment, a separate photoresist mask may be patterned over the matrix to selectively expose metal in inter-package regions to chemical etching.
摘要翻译：作为公共矩阵的一部分制造的单个电子封装的分割是通过掩模图案化和化学暴露与物理锯切结合来实现的。在根据本发明的切割工艺的一个实施例中，切割成基体的封装间区域的初始的浅锯将暴露下面的金属到随后的化学蚀刻步骤。在替代实施例中，单独的光致抗蚀剂掩模可以在基体上图案化以选择性地将包装区域中的金属暴露于化学蚀刻。

8. 发明申请

WO2002093645A1 IMPROVED SURFACE MOUNT PACKAGE 审中-公开
标题翻译：改进的表面安装包
公开(公告)号：WO2002093645A1
公开(公告)日：2002-11-21
申请号：PCT/US2002/014616
申请日：2002-05-09
申请人： GEM SERVICES INC.
发明人： HARNDEN, James , WILLIAMS, Richard, K. , CHIA, Anthony , WEIBING, Chu
IPC分类号： H01L23/48
CPC分类号： H01L24/48 , H01L23/3107 , H01L23/49555 , H01L23/49562 , H01L23/49575 , H01L24/49 , H01L2224/05554 , H01L2224/05647 , H01L2224/0603 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48257 , H01L2224/48464 , H01L2224/49111 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01031 , H01L2924/01047 , H01L2924/01055 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H05K3/3426 , Y02P70/613 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments (630), packages having leads of a reverse gull wing shape (632) reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body (634) and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile (Zprofile) by featuring recesses (636) for receiving lead feet ends (632a), thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.
摘要翻译：微电子器件的节省空间的封装允许每单位PC板表面积更大的功能。在某些实施例（630）中，具有反向鸥翼形状（632）的引线的封装减少了由引线占据的外围覆盖区域，从而允许封装封装中的最大空间分配给封装主体（634）和封装死。根据本发明的封装的实施例还可以通过设置用于接收引脚端部（632a）的凹部（636）来减小封装垂直轮廓（Zprofile），从而减少封装底部和PC板之间的间隙。在封装下面提供一个线性引脚并相对于PC板略微倾斜，通过消除与J型引线的曲率半径相关联的附加间隙，进一步降低了垂直封装形状。

9. 发明申请

WO2005112102A3 CHEMICAL-ENHANCED PACKAGE SINGULATION PROCESS 审中-公开
公开(公告)号：WO2005112102A3
公开(公告)日：2005-11-24
申请号：PCT/US2005/016482
申请日：2005-05-10
申请人： GEM SERVICES, INC. , YILMAZ, Hamza , CHIA, Anthony , ZENG, Xiaoguang , WONG, Hie Ming , WANG, Liming , ZHANG, Yiju
发明人： YILMAZ, Hamza , CHIA, Anthony , ZENG, Xiaoguang , WONG, Hie Ming , WANG, Liming , ZHANG, Yiju
IPC分类号： H01L21/301
摘要： Singulation of individual electronic packages fabricated as part of a common matrix, is accomplished by mask patterning and chemical exposure in combination with physical sawing. In one embodiment of a singulation process in accordance with the present invention, an initial, shallow saw cut into inter-package regions of the matrix exposes underlying metal to subsequent chemical etching steps. In an alternative embodiment, a separate photoresist mask may be patterned over the matrix to selectively expose metal in inter-package regions to chemical etching.

10. 发明申请

WO2004064110A3 SPACE-EFFICIENT PACKAGE FOR LATERALLY CONDUCTING DEVICE 审中-公开
标题翻译：用于横向导电装置的空间高效包装
公开(公告)号：WO2004064110A3
公开(公告)日：2005-07-21
申请号：PCT/US0340543
申请日：2003-12-18
申请人： GEM SERVICES INC
发明人： HARNDEN JAMES , LAM ALLEN K , WILLIAMS RICHARD K , CHIA ANTHONY , CHU WEIBING
IPC分类号： H01L23/495 , H01L21/00 , H05K7/20
CPC分类号： H01L23/49562 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/014 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Efficient utilization of space in a laterally-conducting semiconductor device package (300) is enhanced by creating at least one supplemental downbond pad portion (311) of the diepad (308) for receiving the downbond wire (312) from the ground contact (314) of the device. The supplemental diepad portion (311) may occupy area at the end or side of the package formerly occupied by non-integral leads (306d-h). By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die (302) having a larger area, thereby enhancing space efficiency of the package.
摘要翻译：通过创建用于从接地触头（314）接收下焊接线（312）的平台（308）的至少一个补充的下焊垫部分（311）来增强横向导电的半导体器件封装（300）中的空间的有效利用，的设备。补充的双面部分（311）可以占据以前由非整体引线（306d-h）占据的包装的端部或侧面的区域。通过接收衬底下焊接线，补充的双面部分允许主单区的更大面积被具有较大面积的模具（302）占据，从而提高了封装的空间效率。

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