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1. 发明专利

JP2005190651A Integrated circuit provided with memory in which power consumption is reduced, and control method of integrated circuit in standby mode 审中-公开
标题翻译：集成电路提供减少功耗的存储器，以及备用模式下集成电路的控制方法
公开(公告)号：JP2005190651A
公开(公告)日：2005-07-14
申请号：JP2004374920
申请日：2004-12-24
申请人： Dolphin Integration , ドルフィンインテグレーション
发明人： BONZO ANDREA , POLLET JEAN FRANCOIS
IPC分类号： G11C11/413 , G06F1/32 , G11C5/14 , G11C7/22 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： G11C7/22 , G11C5/14
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit in which power consumption can be reduced in a non-operation mode of the integrated circuit while surely keeping data stored in a volatile memory element, in the integrated circuit provided with a volatile memory element and a logical interface circuit.
SOLUTION: In the integrated circuit provided with a volatile memory element and a logical interface circuit connected to the volatile memory element, first and second power sources are prepared separately, the first power source is connected to the volatile memory element, and the second power source is connected to the logical interface circuit.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种集成电路，其中可以在集成电路的非操作模式中降低功耗，同时确保将存储在易失性存储器元件中的数据保存在设置有易失性存储器的集成电路中元件和逻辑接口电路。解决方案：在具有易失性存储元件和连接到易失性存储器元件的逻辑接口电路的集成电路中，分别准备第一和第二电源，第一电源连接到易失性存储器元件，并且第二电源连接到逻辑接口电路。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JPH1056083A MEMORY ARRAY HAVING ROWS AND COLUMNS CROSSING EACH OTHER SUBSTANTIALLY AT RIGHT ANGLES 失效
公开(公告)号：JPH1056083A
公开(公告)日：1998-02-24
申请号：JP14140697
申请日：1997-05-30
申请人： DOLPHIN INTEGRATION SA
发明人： ZANGARA LOUIS
IPC分类号： H01L21/8246 , H01L27/112
摘要： PROBLEM TO BE SOLVED: To enable a memory array to be programmed by metallization and besides, make it very elaborate by connecting a first island to a first column and a second island to a second column thereby materializing an active transistor. SOLUTION: Activated columns are separated from one another with thick oxides. The rows Li and Li+1 of polysilicon extend to above a thick oxide on one hand and to above the thin oxide region made on an active region on the other, at a fixed interval. Next, n-type implant is applied to this structure to form a second conductivity type of island 21 within an active column between gate regions. Then, it is coated for flattening. The island 21 is connected to the pad 23 on the level of first metallization by a via 22. The pad 23 is connected to the higher level 25 of metallization corresponding to an arrow Cj by a via 24, or it is connected to the metallization on the same level constituting a reference column.

3. 发明专利

JP2002305440A METHOD FOR FRACTIONAL DIVISION OF FREQUENCY OF DIGITAL SIGNAL AND FREQUENCY DIVIDER 审中-公开
公开(公告)号：JP2002305440A
公开(公告)日：2002-10-18
申请号：JP2002022305
申请日：2002-01-30
申请人： DOLPHIN INTEGRATION SA
发明人： POULLET FREDERIC
IPC分类号： H03K21/00 , G06F7/68 , H03K23/68 , H03L7/183
摘要： PROBLEM TO BE SOLVED: To provide a programmable fractional division of frequency for performing fractional frequency division of a digital signal capable of improving solution, and realizing resolution step of 1/N (N is a non-zero natural integer). SOLUTION: At conducting of the fractional frequency division of a digital signal from the N replicas of a digital signal, when phases are shifted by 2π/N, the first replica is selected for generating the rising edge, and the second replica is selected for generating the falling edge, and the first and second replicas of the cycle of the signal to be obtained as a result are made different from the first and second replicas to be used for the next cycle. Also, the second copy of this present cycle forms the first replica of the next cycle, and selects the replica, so that the edge of the second replica valid for the present cycle can appear behind the edge of the first replica in the same type of the present cycle.

4. 发明专利

JPH10190364A LOW NOISE ARRANGEMENT FOR AMPLIFIER 失效
公开(公告)号：JPH10190364A
公开(公告)日：1998-07-21
申请号：JP29056197
申请日：1997-10-08
申请人： DOLPHIN INTEGRATION SA
发明人： COMPAGNE ERIC
IPC分类号： H03F1/26 , H03F1/34 , H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide an integration arrangement realized from an amplifier which suppresses the influence of an output signal against noise to a minimum and has a high gain by containing main amplifiers and a means for generating floating reference voltage for adding an input signal to the first input terminal of the main amplifier and making reference voltage to arrangement which is servo-controlled by the equivalent input noise of the main amplifier. SOLUTION: The main amplifiers 1 and 1' and the means 5 for generating floating reference voltage VG for adding one input signal V' to one first input terminal E- or E in the main amplifiers in a prescribed period are contained. The reference voltage VG is arranged so that it is servo-controlled by the equivalent input noise Vn of the main amplifier 1. The number of cascade-type transistor stages constituting the main amplifier 1 is suppressed to a minimum and the high open loop gain can be obtained. Noise Vn depending on the number of the transistors of the main amplifier 1 is suppressed to a minimum and minimum supply voltage required for the operation of the arrangement can be dropped.

5. 发明专利

JPH06141464A SELF-PROTECTIVE VOLTAGE-DIVIDING BRIDGE 失效
公开(公告)号：JPH06141464A
公开(公告)日：1994-05-20
申请号：JP8953893
申请日：1993-03-25
申请人： DOLPHIN INTEGRATION SA
发明人： ERITSUKU KONPAANIYU
IPC分类号： H02H9/04 , H01L27/02
摘要： PURPOSE: To obtain a self-protected voltage dividing bridge for protecting an integrated circuit itself from overvoltages applied to its terminals. CONSTITUTION: There are provided a P -type substrate 12, an N -type well 11, and a P-type diffusion region 10 obtained by forming a resistance in the well 11 through diffusion. In an outermost portion present above the diffusion region 10, first and second contacts (A), (B) are formed to form an intermediate contact (C) between them. An external voltage VH higher than the supply voltage of an integrated circuit is applied to a pad connected with the first contact A, and a reference voltage source VSS of the integrated circuit is applied to the second contact B and the substrate 12. A third contact (D) formed in the well portion 11 near the first contact A is connected with the first contact A, and a fourth contact (E) formed in the well portion 11 near the second contact B is connected with the second contact B.

6. 发明专利

JP2006345524A CONVERTER AND CONVERSION METHOD 审中-公开
公开(公告)号：JP2006345524A
公开(公告)日：2006-12-21
申请号：JP2006157780
申请日：2006-06-06
申请人： DOLPHIN INTEGRATION SA
发明人： POULET FREDERIC , COGNIARD GUILLAUME
IPC分类号： H03M1/82 , H03M1/08
摘要： PROBLEM TO BE SOLVED: To provide a converter and a conversion method using the same with which a pulse-width modulated signal having a high signal-to-noise ratio can be provided. SOLUTION: A converter to convert a digital signal into a pulse-width modulated signal comprises: a first conversion part receiving, at a first frequency, successive digital signals each having one of a first predetermined number of values, and providing first intermediary signals, at the first frequency, each having one of a second determined number of values smaller than the first predetermined number; a decimation part performing decimation of the first intermediary signals to provide second intermediary signals at a second frequency equal to the frequency obtained by dividing the first frequency by a number obtained by subtracting one from the second predetermined number; and a second conversion part providing at the second frequency, from the second intermediary signals, a two-state pulse-width modulated signal having a minimum duration which is equal to the inverse of the first frequency in one of the two states, and received by the first conversion part. COPYRIGHT: (C)2007,JPO&INPIT

7. 发明专利

JP2008022554A Data flow adapter 审中-公开
标题翻译：数据流适配器
公开(公告)号：JP2008022554A
公开(公告)日：2008-01-31
申请号：JP2007181404
申请日：2007-07-10
申请人： Dolphin Integration , ドルフィンインテグレーション
发明人： LEGRAY FRANCIS , RENANE SALIM
IPC分类号： H04L7/00
CPC分类号： H03H17/0621 , H03H17/0628
摘要： PROBLEM TO BE SOLVED: To provide an adapter circuit which accepts first data at a rate of a first request signal and sends out second data corresponding to the first data at a rate of a second request signal. SOLUTION: The adapter circuit is provided with a controller which generates control data indicating one of three commands which can be modified at the rate of the first request signal, a processor which sends out a third request signal on the basis of the first request signal and the control data and subjects the third request signal to activation zero time, once or twice at each time of the activation of the first request signal according to the control data and a FIFO memory which stores a first data value for each time of the activation of the third request signal which can be processed and sends out second data at each time of the activation of the second request signal. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供以第一请求信号的速率接收第一数据的适配器电路，并且以第二请求信号的速率发送与第一数据相对应的第二数据。适配器电路设置有控制器，其产生指示可以以第一请求信号的速率修改的三个命令之一的控制数据;处理器，其基于第一请求信号发送第三请求信号请求信号和控制数据，并根据控制数据使第三请求信号激活零时间，每次激活第一请求信号时一次或两次;以及FIFO存储器，其每次存储第一数据值激活可以被处理的第三请求信号，并且在激活第二请求信号的每个时间发出第二数据。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2003152112A MEMORY PROVIDED WITH SHARED BIT LINES 审中-公开
公开(公告)号：JP2003152112A
公开(公告)日：2003-05-23
申请号：JP2002247169
申请日：2002-08-27
申请人： DOLPHIN INTEGRATION SA
发明人： COVAREL HERVE , GAUBERT SEBASTIEN
IPC分类号： G11C11/41 , G11C8/14 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To provide a memory whose surface area does not change even in the case of an increase in the number of word lines. SOLUTION: A memory block comprises a network of memory cell rows and columns, and each memory cell is connected to a word line and at least one bit line. At least two word lines are associated with each row, and at least two adjacent columns share at least a same bit line. The memory block is connected to two different word lines in the aforementioned two adjacent columns belonging to the same row.

9. 发明申请

WO2018060584A1 CIRCUIT AUDIO ET PROCEDE DE DETECTION D'ACTIVITE SONORE 审中-公开
标题翻译：音频电路和声音活动检测方法
公开(公告)号：WO2018060584A1
公开(公告)日：2018-04-05
申请号：PCT/FR2017/052581
申请日：2017-09-26
申请人： DOLPHIN INTEGRATION
发明人： GRAND, Emmanuel
IPC分类号： G10L25/78 , H03G3/34 , G06F1/32 , H04W52/02
摘要： L'invention concerne un circuit de détection d'activité sonore comprenant : un transducteur (106) adapté à générer un signal électrique (I AUDIO , V AUDIO ) sur la base de son détecté; un amplificateur à gain variable (122) adapté à amplifier le signal électrique pour générer un signal électrique amplifié; un comparateur (124) adapté à comparer le signal électrique amplifié à au moins un premier niveau de seuil (TH1) pour générer un signal de comparaison (COMP) indiquant des événements de comparateur; et un circuit de commande (126) adapté à générer, sur la base du signal de comparaison (COMP), un signal de contrôle de gain (GAIN) pour contrôler le gain de l'amplificateur à gain variable (122), et un signal d'alerte d'activité sonore (S) indiquant la détection d'activité sonore.
摘要翻译：本发明涉及用于检测活动的电路。声音系统，包括：适配的换能器（106）; ＆Agrave; 根据检测结果产生一个电信号（I _{AUDIO ，V}

10. 发明申请

WO2009019273A1 MEMORY COMPRISING NON-VOLATILE PORTION 审中-公开
标题翻译：包含非挥发性部分的记忆
公开(公告)号：WO2009019273A1
公开(公告)日：2009-02-12
申请号：PCT/EP2008/060282
申请日：2008-08-05
申请人： DOLPHIN INTEGRATION , ZANGARA, Louis , LEROY, Fabien
发明人： ZANGARA, Louis , LEROY, Fabien
IPC分类号： G11C11/00 , G11C7/20 , G11C7/18
CPC分类号： G11C11/419 , G11C7/1006 , G11C14/00 , G11C15/04
摘要： The invention concerns a memory having an array of memory cells (1002) arranged in rows and columns, each being capable of storing at least one first bit of data and comprising an output arranged to output said at least one first bit of data; a plurality of groups of bit lines (1004), each group of bit lines being associated with one of said rows or columns of memory cells, the output of each memory cell being connected to at least one bit line of a group of bit lines, said connection indicating at least one second bit of data, said second bit of data being non-volatile; and output circuitry (1006) coupled to said groups of bit lines and comprising detection circuitry arranged to determine said first and second bits, and logic circuitry arranged to perform a logic function on said first and second bits.
摘要翻译：本发明涉及具有以行和列排列的存储单元阵列（1002）的存储器，每个存储器单元能够存储至少一个第一数据位，并且包括被输出以输出所述至少一个第一数据位的输出; 多个位线组（1004），每组位线与存储器单元的所述行或列之一相关联，每个存储单元的输出连接到一组位线的至少一个位线，所述连接指示至少一个第二位数据，所述第二位数据是非易失性的; 以及耦合到所述位线组的输出电路（1006），并且包括布置成确定所述第一和第二位的检测电路以及布置成在所述第一和第二位上执行逻辑功能的逻辑电路。

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