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1. 发明申请

WO9920006A3 SINGLE-CHIP AUDIO CIRCUITS, METHODS, AND SYSTEMS USING THE SAME 审中-公开
标题翻译：单片音频电路，方法和使用它的系统
公开(公告)号：WO9920006A3
公开(公告)日：1999-08-26
申请号：PCT/US9820898
申请日：1998-10-01
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： MALCOLM RONALD D JR , KLAAS JEFF , GENTRY MARK , MATTHEWS PHILLIP
IPC分类号： G06F3/16 , H03L3/00 , H04H60/04 , H04H5/00 , H03G3/00 , H03K3/03 , H04S1/00
CPC分类号： G06F3/165 , H03L3/00 , H04H60/04
摘要： A single chip audio system (100) includes a bus interface (101), digital to analog converters (110), an analog mixer (115), and anolog spatial enhancement circuitry (7500). Digital to analog converters (110) convert digital audio data received through bus interface (101) into analog signals. Analog mixer (115) mixes signals received from digital to analog converters (110) with an analog signal received from an external source. Analog spatial enhancement circuitry (7500) enhances first and second mixed analog signals output from analog mixer (115).
摘要翻译：单芯片音频系统（100）包括总线接口（101），数模转换器（110），模拟混合器（115）和模仿空间增强电路（7500）。数模转换器（110）将通过总线接口（101）接收的数字音频数据转换为模拟信号。模拟混频器（115）将从数模转换器（110）接收的信号与从外部源接收的模拟信号混合。模拟空间增强电路（7500）增强了从模拟混频器（115）输出的第一和第二混合模拟信号。

2. 发明专利

DE4203879C2 未知
公开(公告)号：DE4203879C2
公开(公告)日：1998-07-02
申请号：DE4203879
申请日：1992-02-11
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： KERTH DONALD ALLAN , SOOCH NAVDEEP SINGH
IPC分类号： G01R19/00 , G01D3/00 , G01R19/10 , G01R19/25 , H03M1/06 , H03M1/12 , H03M3/00 , G01D5/14 , G01R17/00 , G01R15/00 , H03H17/00
摘要： A ratiometric converter receives an external sense signal and external reference signal and provides an output signal which is proportional to the sense signal and inversely proportional to the reference signal. Electromagnetic interference and noise coupled onto the sense and reference lines are effectively removed by converting the sense signal to a digital signal and converting the reference signal to a digital signal. The digital sense signal is then filtered through a low pass filter to provide a filtered signal, and similarly, the digital reference signal is filtered through a low pass filter to provide a filtered digital reference signal. A divider circuit then divides the filter digital sense signal by the filter digital reference signal to provide the output signal.

3. 发明专利

GB9514965D0 Amplifier 未知
公开(公告)号：GB9514965D0
公开(公告)日：1995-09-20
申请号：GB9514965
申请日：1992-03-31
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H03M3/02

4. 发明专利

GB2265283A RESYNCHRONIZATION OF A SYNCHRONOUS SERIAL INTERFACE 未知
公开(公告)号：GB2265283A
公开(公告)日：1993-09-22
申请号：GB9303715
申请日：1993-02-24
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： SANCHEZ CLIFTON W
IPC分类号： H04L7/00 , G06F13/42 , H04L7/08 , H04L7/10 , H04L25/40 , H04L25/45 , H04L29/08

5. 发明专利

DE4300519A1 未知
公开(公告)号：DE4300519A1
公开(公告)日：1993-07-22
申请号：DE4300519
申请日：1993-01-12
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： SCOTT JEFFREY WILLIAM
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/08 , H01L29/92 , H03H19/00
摘要： A tri-level capacitor structure includes a first shielded metal layer (36) that is disposed between an upper metal layer (38) and a lower polysilicon layer (34). The shielded metal layer (36) is separated from the polysilicon layer (34) by an oxide layer (42), and the upper metal layer (38) is separated from the shielded layer (36) by an oxide layer (44). The upper metal layer (38) and the polysilicon layer (34) are connected together to a node (48) to form an Insensitive Node, whereas the shielded layer (36) is connected to a node (46) that is referred to as the Sensitive Node (S). The capacitor structure is operable to be connected in a switched-capacitor configuration in a lossy integrator, such that the Sensitive Node is connected to the virtual ground of a differential amplifier (50). The integrator utilizing this configuration would be comprised of at least one switched-capacitor (56) on the input that has the plates thereof connected between ground and either an input signal VIN or the inverting input of the differential amplifier (50) through control switches (62) and (64). The Sensitive Node associated with node (46) is connected to the switch (62) such that it is connected between ground and the inverting input of amplifier (50).

6. 发明专利

DE4220012A1 未知
公开(公告)号：DE4220012A1
公开(公告)日：1992-12-24
申请号：DE4220012
申请日：1992-06-19
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： KERTH DONALD ALLAN , PIASECKI DOUGLAS SCOTT
IPC分类号： H03M1/10 , G01D3/00 , H03M1/06 , H03M1/12 , H03M3/00 , H03M3/02
摘要： A ratiometric converter includes first and second A/D converters (36, 38). The latter receives an input signal voltage from a load cell (10) on sense lines (12) and (14) and compares it with an internal reference. Similarly, the first converter (36) receives the reference voltage to the load cell (10) and compares it with the internal reference. The outputs of the converters (36) and (38) are then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) short the reference nodes in the load cell (10) together to determine the non- ratiometric offsets VOFF1-4. These offsets are stored in registers (80) and (86) for the reference and input voltages, respectively. During operation, the offsets are input to subtraction blocks (78) and (84) and a digital subtraction performed on the outputs of both converters. The outputs of the subtraction blocks (78) and (84) are input to a ratio metric operator block (52) to perform a digital division thereon. This results in a ratiometric output that has the non-ratiometric offsets removed. Thereafter, the signal is input to a system calibration block (32) to remove ratiometric errors.

7. 发明专利

DE4218533A1 未知
公开(公告)号：DE4218533A1
公开(公告)日：1992-12-10
申请号：DE4218533
申请日：1992-06-05
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： KERTH DONALD ALLAN
IPC分类号： H03F3/38 , G06G7/186 , H03H19/00 , H03M3/02
摘要： A switched-capacitor integrator (10) with chopper stabilization performed at the sampling rate virtually eliminates the flicker noise and any low frequency interference generated by the amplifier (12). The integrator samples the input and then passes the sampled input to the feedback capacitor (14) during each chopping phase of the amplifier to thereby provide a double-sampled integrator. The output of the integrator is sampled at the end of each cycle of the chopping signal.

8. 发明专利

GB9217800D0 A FOURTH ORDER DIGITAL DELTA-SIGMA MODULATOR 未知
公开(公告)号：GB9217800D0
公开(公告)日：1992-10-07
申请号：GB9217800
申请日：1992-08-21
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H03M3/02 , H03M7/32
摘要： A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4x clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70). This represents the operation of the second stage of integration. The output of register (64) represents the output of each stage of integration after the accumulation step, which is then input to one of four shift left registers (82)-(88), which performs a gain scaling function. An overflow condition is also accommodated with an exclusive-OR gate (78).

9. 发明专利

GB2252829A Method and apparatus for decreasing the interference and noise sensitivity of a ratiometric converter type of circuit 未知
公开(公告)号：GB2252829A
公开(公告)日：1992-08-19
申请号：GB9202341
申请日：1992-02-04
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： KERTH DONALD ALLAN , SOOCH NAVDEEP SINGH
IPC分类号： G01R19/00 , G01D3/00 , G01R19/10 , G01R19/25 , H03M1/06 , H03M1/12 , H03M3/00
摘要： A ratiometric converter (12) receives a sense signal AIN+, AIN- and a reference signal VREF+(EXT), VREF-(EXT) and provides an output signal COUT which is proportional to the sense signal and inversely proportional to the reference signal. Electromagnetic interference and noise coupled onto the sense and reference lines are effectively removed by converting the sense and reference signals to digital signals and filtering through digital filters (22, 30).A divider circuit (24) then divides the filtered digital sense signal by the filtered digital reference signal to provide the output signal.

10. 发明专利

DE4200745A1 未知
公开(公告)号：DE4200745A1
公开(公告)日：1992-07-16
申请号：DE4200745
申请日：1992-01-14
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： SCOTT JEFFREY WILLIAM
IPC分类号： H03F1/32 , H03F3/30 , H03F3/343 , H03F3/45 , H03H19/00 , H03M1/08 , H03M1/66 , H03M3/02
摘要： A unity gain buffer for a DAC is provided that is disposed on the output of a switched-capacitor filter and sampled data/continuous time buffer. The unity gain buffer provides low-distortion operation with a high input impedance. Differential input transistors (190) and (200) are provided having the source thereof connected to a common source node (202). A current source transistor (214) provides a current source between node (202) and ground. Each of the drains of transistors (190) and (200) have a constant current source provided thereto by transistors (222) and (230). Cascode devices (216) and (226) are disposed in the drains of transistors (190) and (200) to maintain a constant VDS during large input common-mode conditions. Any bias variations in transistor (214) are absorbed by feedback transistors (232) and (234), which provide a variable current source to node (202). These are controlled by the voltages on the drains of transistors (190) and (200).

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