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2. 发明专利

JP6738827B2 マルチチップのダイナミックレンジ拡張(DRE)音声処理の方法および装置有权
公开(公告)号：JP6738827B2
公开(公告)日：2020-08-12
申请号：JP2017550521
申请日：2016-03-16
申请人：シーラスロジック,インコーポレイテッド , Cirrus Logic,Inc.
发明人：ダス、テジャスヴィ , メランソン、ジョンエル.
IPC分类号： H04R3/00 , H03G7/00

3. 发明专利

JP2011216182A Fault tolerant sync mark detector improved for sampled amplitude magnetic recording 审中-公开
标题翻译：用于采样放大磁记录改进的容错同步标记检测器
公开(公告)号：JP2011216182A
公开(公告)日：2011-10-27
申请号：JP2011144396
申请日：2011-06-29
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： ZOOK CHRISTOPHER P
IPC分类号： G11B20/14 , G11B5/012 , G11B20/10 , G11B27/30
CPC分类号： G11B20/10055 , G11B5/012 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B27/30 , G11B27/3027 , G11B2020/1476
摘要： PROBLEM TO BE SOLVED: To provide a sync mark detecting method for using information from a preamble and codes of sampled data to increase the fault tolerance of a sync mark detector.SOLUTION: Digital data have a preamble field, the following synchronization mark succeeding to the field, and a data field succeeding to the mark. The timing recovery (28) of a reading channel synchronizes a phase and a frequency of the preamble field, and a synchronization detector (A120) detects the synchronization mark and frames an operation of an RLL decoder (36, A122) for decoding the detected data field. The synchronization mark is selected to meet conditions that a correlation with the shifted synchronization mark connected to the preamble field is minimum in order to reduce a possibility of early erroneous detection. The synchronization mark detector is enabled by timing recovery relative to the end of the preamble field in order to further increase the fault tolerance.
摘要翻译：要解决的问题：提供一种同步标记检测方法，用于使用来自前导码的信息和采样数据的代码来增加同步标记检测器的容错。解决方案：数字数据具有前导字段，后面的同步标记字段和跟随标记的数据字段。读取通道的定时恢复（28）同步前同步码字段的相位和频率，同步检测器（A120）检测同步标记，并对RLL解码器（36，A122）的操作进行成帧，以解码检测到的数据领域。选择同步标记以满足与连接到前导字段的移位同步标记的相关性最小的条件，以便减少早期错误检测的可能性。同步标记检测器通过相对于前导码字段的结尾的定时恢复来启用，以便进一步增加容错。

4. 发明专利

JP2009217927A Sliding mode control of magnetoresistive read head for magnetic recording 有权
标题翻译：用于磁记录的磁化读取头的滑动模式控制
公开(公告)号：JP2009217927A
公开(公告)日：2009-09-24
申请号：JP2009115063
申请日：2009-05-11
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： ROMANO PAUL M , SUPINO LOUIS
IPC分类号： G11B21/08 , G11B21/10 , G11B5/00 , G11B5/55 , G11B5/596
CPC分类号： G11B5/59683 , G11B5/5547 , G11B2005/0016
摘要： PROBLEM TO BE SOLVED: To provide a low-cost, more efficient magnetic disk servo control system that compensates for non-linear gain variations associated with MR read heads.
SOLUTION: A position error X149 is multiplied by a positive gain 47 or a negative gain 48 depending on the state of a switch 46 to generate an acceleration command U53 as input to the controlled system 44. The output of an integrator 54 is the velocity of a controlled system which is also the negative -X255 of the position error velocity. When the switch 46 selects the positive gain 47, it is a negative feedback system, and when the switch 46 selects the negative gain 48, it is a positive feedback system. In each of the structures, the system is unstable. However, the system can be made stable by repeatedly switching between the two structures.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种低成本，更高效的磁盘伺服控制系统，其补偿与MR读取头相关联的非线性增益变化。解决方案：位置误差X149根据开关46的状态乘以正增益47或负增益48，以产生加速指令U53作为对受控系统44的输入。积分器54的输出为受控系统的速度也是位置误差速度的负-X255。当开关46选择正增益47时，它是负反馈系统，并且当开关46选择负增益48时，它是正反馈系统。在每个结构中，系统不稳定。然而，可以通过在两个结构之间重复切换来使系统变得稳定。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008160843A Sample and hold circuits and methods with offset error correction and systems using the same 审中-公开
标题翻译：使用偏移校正和校正的系统进行采样和保持电路和方法
公开(公告)号：JP2008160843A
公开(公告)日：2008-07-10
申请号：JP2007328033
申请日：2007-12-19
申请人： Cirrus Logic Inc , シラスロジック、インコーポレイテッド
发明人： PRASAD AMMISETTI V , THOMPSON KARL , MELANSON JOHN LAURENCE , SOMAYAJULA SHYAM
IPC分类号： H03M1/12 , G11B20/10 , G11C27/02 , H03K17/00
CPC分类号： G11C27/024
摘要： PROBLEM TO BE SOLVED: To provide a sample and hold circuit suitable for mixed signal processing.
SOLUTION: A sample and hold circuit includes a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor, and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供适用于混合信号处理的采样和保持电路。解决方案：采样和保持电路包括用于存储输入信号的采样的采样电容器，用于输出存储在采样电容器上的采样的输出级，以及用于对输入信号进行采样并将样本存储在采样电容器。输入电路包括自动调零输入缓冲器，其在第一操作阶段期间选择性地采样输入信号，并且在第二操作阶段期间保持输入信号的采样。自动归零输入缓冲器取消任何偏移误差。输入电路还包括用于在第二操作阶段期间将采样电容器与采样和保持电路的输入有选择地耦合的开关电路，以及在第一操作阶段期间自动调零输入缓冲器的输出。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007080514A Improved fault tolerant sync mark detector for sampled amplitude magnetic recording 审中-公开
标题翻译：改进的容错同步标记检测器，用于采样放大磁记录
公开(公告)号：JP2007080514A
公开(公告)日：2007-03-29
申请号：JP2006340551
申请日：2006-12-18
申请人： Cirrus Logic Inc , シラスロジック、インコーポレイテッド
发明人： ZOOK CHRISTOPHER P
IPC分类号： G11B20/14 , G11B5/012 , G11B20/10 , G11B27/30
CPC分类号： G11B20/10055 , G11B5/012 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B27/30 , G11B27/3027 , G11B2020/1476
摘要： PROBLEM TO BE SOLVED: To provide a sync mark detection method that uses information from a preamble and the sign of sampled data in order to further increase the fault tolerance of a sync mark detector.
SOLUTION: Digital data comprise a preamble field followed by a sync mark followed by a data field. Timing recovery (28) in a read channel synchronizes to a phase and frequency of the preamble field and a sync detector (A120) detects the sync mark in order to frame operation of an RLL decoder (36, A122) for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to the end of the preamble field.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供使用来自前导码的信息和采样数据的符号的同步标记检测方法，以进一步增加同步标记检测器的容错性。解决方案：数字数据包括前同步码字段，随后是同步标记，后跟数据字段。读通道中的定时恢复（28）与前同步码字段的相位和频率同步，并且同步检测器（A120）检测同步标记，以便对RLL解码器（36，A122）进行帧操作，以解码检测到的数据字段。为了降低早期错误检测的可能性，选择同步标记与与前导字段连接的同步标记的移位版本具有最小相关性。为了进一步增加容错能力，同步标记检测器通过相对于前同步码字段结束的定时恢复来启用。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2005050519A Voice coil motor control circuit and method 有权
标题翻译：语音线圈电机控制电路及方法
公开(公告)号：JP2005050519A
公开(公告)日：2005-02-24
申请号：JP2004265484
申请日：2004-09-13
申请人： Cirrus Logic Inc , サーラス・ロジック・インコーポレーテッド
发明人： ROMANO PAUL M
IPC分类号： G11B5/596 , G11B5/54 , G11B21/12 , H02P25/06 , H02P5/00
CPC分类号： G11B5/54
摘要： PROBLEM TO BE SOLVED: To provide a voice coil motor control circuit and a method. SOLUTION: The voice coil motor (VCM) control circuit (10) controls a motor operation to position a disk drive head and actuator arm assembly (202). A data processor (220) is continuously updated with the current position and relative radial velocity of the disk drive head (206) and actuator arm assembly (208). The data processor (220) provides signals to a digital-analog converter (DAC) of the VCM control circuit (10) representative of the amount of energy necessary to move the head and actuator arm assembly to a parking position from a current operating position. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种音圈电机控制电路及方法。解决方案：音圈电机（VCM）控制电路（10）控制电动机操作以定位盘驱动头和致动器臂组件（202）。数据处理器（220）以盘驱动头（206）和致动器臂组件（208）的当前位置和相对径向速度连续地更新。数据处理器（220）向VCM控制电路（10）的数模转换器（DAC）提供代表将头部和致动器臂组件从当前操作位置移动到驻车位置所需的能量的量。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JPH11149649A DIFFERENTIAL PHASE ERROR DETECTOR, AND DIFFERENTIAL METHOD GENERATING A TRACKING ERROR SIGNAL BY DETECTING PHASE ERROR 失效
公开(公告)号：JPH11149649A
公开(公告)日：1999-06-02
申请号：JP22830698
申请日：1998-08-12
申请人： CIRRUS LOGIC INC
发明人： FEYH GERMAN S , SPINO LOUIS , PAUL ROMANO , LARRY KING
IPC分类号： G11B7/085 , G11B7/09
摘要： PROBLEM TO BE SOLVED: To generate a position error signal independently of a frequency component of recorded data in a differential phase detector for an optical disk recording device. SOLUTION: One pair of diagonal signals S1 and S2 are generated by adding each quadrant A-D of a quadripartite detector. Phase offset among these diagonal signals indicate a position error of an image of a pit at a point of time at which a image of a pit passes through an optical detector. This position error is obtained by calculating a difference between positive correlation and negative correlation of diagonal signals S1 and S2 which are called as dual arm correlation(DAC). Then, Δ is correlation offset, L is correlation length. In a suitable actual mode, correlation of offset Δ is adjusted to be suitable so that correlation between S1 and S2 is made the maximum.

9. 发明专利

JPH10340129A CIRCUIT CONTROLLING POWER USED AMOUNT IN ELECTRONIC SYSTEM AND ITS METHOD 失效
公开(公告)号：JPH10340129A
公开(公告)日：1998-12-22
申请号：JP53198
申请日：1998-01-05
申请人： CIRRUS LOGIC INC
发明人： HILLMAN JOHN , COOKE CHRISTOPHER
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To reduce an power consumption amount by a register by deciding a registers that do not take part in a processing cycle based on the analysis result of each microinstruction and preventing them from being clocked in a processing cycle. SOLUTION: A decode logic 28 examines an appropriate field or a bit position of a microinstruction which is a set of all kinds of bits that control each processing cycle and decides which register 20 takes parts in a certain processing cycle. As for a register 20 which is decided as not taking part in the processing cycle here, a clock signal from a clock source 24 is blocked and the clock signal is prevented from adding to a clock input 21 of the register 20 through a corresponding AND gate 26. That makes it possible to reduce the total used amount of power in a system by reducing the power consumption of an unused register in a certain processing cycle from the power consumption of used registers.

10. 发明专利

JPH10283743A SERVO DECODER 失效
公开(公告)号：JPH10283743A
公开(公告)日：1998-10-23
申请号：JP1625198
申请日：1998-01-28
申请人： CIRRUS LOGIC INC
发明人： RICHARD T BEHRENS , ZOOK CHRISTOPHER P , STEVEN A TARKE , REED DAVID E
IPC分类号： G11B5/55 , G11B5/596 , G11B7/007 , G11B21/08 , G11B21/10 , G11B27/30
摘要： PROBLEM TO BE SOLVED: To enable a servo code format for a high recording density by mapping the detected code word of adjacent tracks to the decoded code word indicating one adjacent track at the time of mapping two detected code words to one decoded code word to seek the selected track with a read head. SOLUTION: This decoder 84 performs the decoding to an effective track address of estimated data sequence even when a readout signal becomes ambiguous due to interference between tracks during the seek operation. That is, a binary track address is coded depending on the coding scheme for correcting random bit error and ambiguity generated as a result of interference between tracks during the seek operation can be solved to overcome the limitation on the servo gray code. After the correction, seven code word bits is mapped to the four information bits in order to decode the code word.

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