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1. 发明申请

WO2008067550A2 DUAL VOLTAGE POWER SUPPLY 审中-公开
标题翻译：双电源
公开(公告)号：WO2008067550A2
公开(公告)日：2008-06-05
申请号：PCT/US2007/086137
申请日：2007-11-30
申请人： CELIS SEMICONDUCTOR CORPORATION , DEVILBISS, Alan D.
发明人： DEVILBISS, Alan D.
IPC分类号： G05F1/10 , H02J7/00
CPC分类号： H02J7/345 , H02M7/06
摘要： A power supply for an integrated circuit has first and second energy storage elements and a regulator. The first energy storage element stores energy for application to the integrated circuit. The second energy storage element stores energy at a higher voltage than the energy stored by the first energy storage element. The regulator interconnects the energy storage elements and controls the flow of energy from the second energy storage element to the first energy storage element to regulate the voltage level of the energy stored in the first energy storage element.
摘要翻译：用于集成电路的电源具有第一和第二能量存储元件和调节器。第一能量存储元件存储用于应用于集成电路的能量。第二能量存储元件将能量存储在比由第一能量存储元件存储的能量更高的电压。调节器将能量存储元件互连并且控制从第二能量存储元件到第一能量存储元件的能量流，以调节存储在第一能量存储元件中的能量的电压电平。

2. 发明申请

WO2003092045A3 METHOD FOR PRODUCING AN ELECTRICAL CIRCUIT 审中-公开
公开(公告)号：WO2003092045A3
公开(公告)日：2003-11-06
申请号：PCT/US2003/012805
申请日：2003-04-25
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DERBENWICK, Gary, F. , DEVILBISS, Alan, D.
IPC分类号： H05K5/00
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate (1), forming and patterning a conductive layer on another substrate (40), depositing a dielectric layer (37) on at least a portion of one of conductive layers (3, 41), mounting an integrated (5) circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.

3. 发明申请

WO2003084072A3 ANALOG-TO-DIGITAL CONVERSION 审中-公开
公开(公告)号：WO2003084072A3
公开(公告)日：2003-10-09
申请号：PCT/US2003/008584
申请日：2003-03-21
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DeVILBISS, Alan, D.
IPC分类号： H03M1/60
摘要： The A/D converter has a voltage controlled current source (16), a capacitor (18), a Schmidt trigger (22), a counter (6), and a transistor switch (20). The analog input voltage controls the voltage controlled current source. The terminal is coupled to the capacitor (18), the transistor (20), and the input of the Schmidt trigger (22). The other terminal of the capacitor (18) and the drain of the transistor (20) are coupled to the input of the counter (6). The output of the Schmidt Trigger is coupled to the input of the counter. The Reset clock (14) is coupled to the reset terminals of the Schmidt trigger (22) and the counter (6). The output of the counter represents the digital equivalent of the analog input.

4. 发明申请

WO2003079305A1 INTEGRATED CIRCUIT WITH ENHANCED COUPLING 审中-公开
标题翻译：集成电路与增强耦合
公开(公告)号：WO2003079305A1
公开(公告)日：2003-09-25
申请号：PCT/US2003/007462
申请日：2003-03-12
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DE VILBISS, Alan, D.
IPC分类号： G08B13/14
CPC分类号： G08B13/2414 , G06K7/0008 , G06K7/10178 , G06K19/07756 , G08B13/2417 , G08B13/2448
摘要： A system for conveying a radio frequency (RF) signal from a base station (16) to a detached integrated circuit (IC) has an intermediate resonant circuit (4) and an IC (2). The intermediate resonant circuit is configured to resonate in response to the RF signal from the base station, reproducing the RF signal. The IC has an integral resonant circuit (6, 8, 10) configured to resonate in response to the reproduced RF signal. The IC and the intermediate resonant circuit are affixed proximate each other. Both are separate from the base station and each other. Either or both of the intermediate resonant circuit and the integral resonant circuit may contact a high magnetic permeability layer. The intermediate resonant circuit may be formed of conductive ink.
摘要翻译：用于将射频（RF）信号从基站（16）传送到分离的集成电路（IC）的系统具有中间谐振电路（4）和IC（2）。中间谐振电路被配置为响应于来自基站的RF信号而谐振，再现RF信号。 IC具有被配置为响应于再现的RF信号而谐振的积分谐振电路（6,8,10）。 IC和中间谐振电路彼此靠近地固定。两者都与基站和彼此分开。中间谐振电路和积分谐振电路中的任一个或两者可以接触高磁导率层。中间谐振电路可以由导电油墨形成。

5. 发明申请

WO2008067546A2 RECTIFIED POWER SUPPLY 审中-公开
标题翻译：整流电源
公开(公告)号：WO2008067546A2
公开(公告)日：2008-06-05
申请号：PCT/US2007/086121
申请日：2007-11-30
申请人： CELIS SEMICONDUCTOR CORPORATION , DEVILBISS, Alan, D.
发明人： DEVILBISS, Alan, D.
IPC分类号： H02J3/24
CPC分类号： G06K7/0008
摘要： A power supply creates a voltage difference between high and low power supply rails. The power supply has a voltage signal source, a capacitive coupling element, energy storage element 12, first and second rectifying diodes, a regulator, and bypass means for selectively decreasing the impedance between the voltage signal source and the low power supply rail or increasing the load presented to the voltage signal source. The capacitive coupling element is connected to the voltage signal source. Energy storage element 12 stores energy between the high and low power supply rails. The first rectifying diode is positioned between the capacitive coupling element and energy storage element 12. It is coupled to the voltage signal source through the capacitive coupling element and arranged to favor current flow toward energy storage element 12 from the capacitive coupling element. The second rectifying diode is positioned between the capacitive coupling element and the low power supply rail. It is coupled to the voltage signal source through the capacitive coupling element and arranged to favor current flow toward the capacitive coupling element from the low power supply rail. The regulator regulates the level of energy stored in energy storage element 12.
摘要翻译：电源在高电源和低电源轨之间产生电压差。电源具有电压信号源，电容耦合元件，能量存储元件12，第一和第二整流二极管，调节器和旁路装置，用于选择性地降低电压信号源和低电源轨之间的阻抗，或增加载入电压信号源。电容耦合元件连接到电压信号源。储能元件12在高电源轨和低电源轨之间存储能量。第一整流二极管位于电容耦合元件和能量存储元件12之间。它通过电容耦合元件耦合到电压信号源，并被布置成有利于从电容耦合元件朝向能量存储元件12的电流。第二整流二极管位于电容耦合元件和低电源轨之间。其通过电容耦合元件耦合到电压信号源，并且被布置成有利于从低电源轨道朝向电容耦合元件的电流。调节器调节存储在储能元件12中的能量水平。

6. 发明申请

WO2003092045A2 METHOD FOR PRODUCING AN ELECTRICAL CIRCUIT 审中-公开
标题翻译：生产电路的方法
公开(公告)号：WO2003092045A2
公开(公告)日：2003-11-06
申请号：PCT/US2003/012805
申请日：2003-04-25
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DERBENWICK, Gary, F. , DEVILBISS, Alan, D.
IPC分类号： H01L
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译：通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层的至少一部分上沉积介电层，将集成电路（IC）安装在衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。内部导电层可以用于将IC耦合到导电层。

7. 发明申请

WO2003084072A2 ANALOG-TO-DIGITAL CONVERSION 审中-公开
标题翻译：模拟到数字转换
公开(公告)号：WO2003084072A2
公开(公告)日：2003-10-09
申请号：PCT/US2003/008584
申请日：2003-03-21
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DeVILBISS, Alan, D.
IPC分类号： H03M1/60
CPC分类号： H03M1/60
摘要： An analog-to-digital (A/D) converter converts an analog input signal to a digital representation. The A/D converter has a voltage controlled current source, a Schmidt trigger, a counter, a capacitor, and a transistor switch. The analog input voltage controls the voltage controlled current source. The negative terminal of the current source is coupled to ground, and the positive terminal is coupled to the capacitor, the transistor, and the input of the Schmidt trigger. The other terminal of the capacitor and the drain of the transistor are coupled to a power supply voltage source. The output of the Schmidt Trigger is coupled to the input of the counter. The Reset clock is coupled to the reset terminals of the Schmidt trigger and the counter. The output of the counter represents the digital equivalent of the analog input.
摘要翻译：模拟数字（A / D）转换器将模拟输入信号转换为数字表示。 A / D转换器具有压控电流源，施密特触发器，计数器，电容器和晶体管开关。模拟输入电压控制电压控制电流源。电流源的负极耦合到地，而正端耦合到电容，晶体管和施密特触发的输入端。电容器的另一个端子和晶体管的漏极耦合到电源电压源。施密特触发器的输出耦合到计数器的输入端。复位时钟耦合到施密特触发器和计数器的复位端子。计数器的输出表示模拟输入的数字等效。

8. 发明申请

WO2003079524A3 RECTIFIER UTILIZING A GROUNDED ANTENNA 审中-公开
公开(公告)号：WO2003079524A3
公开(公告)日：2003-09-25
申请号：PCT/US2003/007474
申请日：2003-03-12
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DEVILBISS, Alan, D. , DERBENWICK, Gary, F.
IPC分类号： H02J9/00
摘要： A rectifier (diodes, 30, 32) generates a rectified output and a do power output (22). The rectifier has an antenna element (24), a tuning capacitor (26), a coupling capacitor (28), first (30) and second (32) rectifying diodes, and a storage capacitor (34). The antenna element (24) and the tuning capacitor (26) are coupled in parallel and grounded at one terminal. The first rectifying diode (30) is grounded at its anode terminal and the storage capacitor (34) is grounded at one terminal. The coupling capacitor (30) is coupled between the ungrounded terminal of the antenna element (24) and the cathode terminal of the first rectifying diode 30). The anode terminal of the second rectifying diode (32) is coupled to the cathode terminal of the first rectifying diode (30). The cathode terminal of the second rectifying diode (32) is coupled to the ungrounded terminal of the storage capacitor (34). The rectifying output is generated between the rectifying diodes (node 20). The dc power output is generated between the second rectifying diode (32) and the storage capacitor (node 22).

9. 发明申请

WO2003079524A2 RECTIFIER UTILIZING A GROUNDED ANTENNA 审中-公开
标题翻译：整流器利用接地天线
公开(公告)号：WO2003079524A2
公开(公告)日：2003-09-25
申请号：PCT/US2003/007474
申请日：2003-03-12
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DEVILBISS, Alan, D. , DERBENWICK, Gary, F.
IPC分类号： H02M
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier generates a rectified output and a do power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.
摘要翻译：整流器产生整流输出和执行功率输出。整流器具有天线元件，调谐电容器，耦合电容器，第一和第二整流二极管以及存储电容器。天线元件和调谐电容器并联耦合并在一个端子处接地。第一个整流二极管在其阳极端子接地，存储电容器在一个端子接地。耦合电容器耦合在天线元件的未接地端子和第一整流二极管的阴极端子之间。第二整流二极管的阳极端子耦合到第一整流二极管的阴极端子。第二整流二极管的阴极端子耦合到存储电容器的未接地端子。整流二极管之间产生整流输出。在第二整流二极管和存储电容器之间产生直流功率输出。

10. 发明申请

WO2008067542A2 ACTIVE RECTIFIER 审中-公开
标题翻译：主动整流器
公开(公告)号：WO2008067542A2
公开(公告)日：2008-06-05
申请号：PCT/US2007/086112
申请日：2007-11-30
申请人： CELIS SEMICONDUCTOR CORPORATION , DEVILBISS, Alan D.
发明人： DEVILBISS, Alan D.
IPC分类号： H02M7/217
CPC分类号： H02M7/217
摘要： A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.
摘要翻译：电压信号整流器从输入偏移电压信号产生整流电压信号。电压信号整流器包括输入偏移，输出和参考节点，两个主动控制的电流调节元件（ACCRE）和两个控制器。输入偏移节点耦合到输入偏移电压信号。整流电压信号被产生到输出节点上。参考节点耦合到用于输入偏移和整流电压信号的参考电压。 ACCRE耦合到输入偏移节点，并且ACCRE中的一个耦合到输出节点。每个控制器被配置为控制ACCRE中的一个，使得当输入偏移电压信号高于整流电压信号时，耦合到输出节点的ACCRE允许电流流过它，而另一个ACCRE被配置为允许电流流过它当输入失调电压信号低于整流电压信号时。

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