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1. 发明专利

JP2010108484A Method and system for design rule checking enhanced with pattern matching 审中-公开
标题翻译：用于图案匹配的设计规则检查方法与系统
公开(公告)号：JP2010108484A
公开(公告)日：2010-05-13
申请号：JP2009201601
申请日：2009-09-01
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズ,インク.
发明人： LAI YA-CHIEH , MOSKEWICZ MATTHEW , GENNARI FRANK
IPC分类号： G06F17/50 , H01L21/82 , H05K3/00
CPC分类号： G06F17/5081
摘要： PROBLEM TO BE SOLVED: To enable circuit designers to waive certain design rules for their circuit designs.
SOLUTION: One embodiment of the invention includes receiving a first layout pattern containing a new layout of an integrated circuit pattern, a pattern matcher 110 processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet design waiver information. The pattern matcher 110 generates a second layout pattern with the waived patterns marked. A design rule checker 115 subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker 115 generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使电路设计人员能够放弃其电路设计的某些设计规则。解决方案：本发明的一个实施例包括接收包含集成电路图案的新布局的第一布局图案，图案匹配器110处理布局图案并且指定符合设计豁免信息的集成电路图案的某些图案。图案匹配器110产生具有标记的放弃图案的第二布局图案。设计规则检查器115随后处理标记的布局图案，并针对一组指定的设计规则验证除了标记的第二布局图案的图案之外的所有图案。设计规则检查器115生成第三布局图案，其中仅针对布图的未标记图案针对指定的设计规则集进行验证。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005039273A Lithographic equipment for semiconductor device, and lithographic method for semiconductor device using the equipment 审中-公开
标题翻译：用于半导体器件的光刻设备和使用设备的半导体器件的平面方法
公开(公告)号：JP2005039273A
公开(公告)日：2005-02-10
申请号：JP2004206973
申请日：2004-07-14
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： SCHEFFER LOUIS , YOSHIDA KENJI , ABE YOSHIKUNI , FUJIMURA AKI , PACK ROBERT
IPC分类号： G03F7/20 , G06F9/45 , G06F9/455 , G06F17/50 , H01L21/027
CPC分类号： G06F17/5068 , G03F1/68
摘要： PROBLEM TO BE SOLVED: To provide a lithographic equipment for a semiconductor device which controls a cost increase and reduction of yield to the minimum and can carry out lithography for a semiconductor device at high speed; and to provide a drawing method for the semiconductor device using the equipment.
SOLUTION: Using information obtained from the "context" of design, a figure of less importance is drawn with lower precision (but at a high speed); and even though its speed may drop significantly, the most important part is drawn by technique being able to secure sufficient precision. As a result of decision on which figure is important among them, they are classified into a plurality of levels. A predetermined level is further decided on the basis of a reference of required precision, classification into a precision higher than the predetermined level, and the precision lower than the predetermined level is carried out by data processing. If the important figure is only a small part of the whole, the method is carried out at a much higher speed, as compared with drawing the whole chip in multi-mode. The remaining figures of less importance can be drawn in a mode using fewer passes.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于半导体器件的光刻设备，其将成本增加和产量降低最小化并且可以高速度地执行半导体器件的光刻; 并提供使用该设备的半导体器件的绘图方法。解决方案：使用从设计的“上下文”获得的信息，以较低的精度（但是高速度）绘制一个不太重要的数字; 即使其速度可能明显下降，最重要的部分是通过能够确保足够的精度的技术来绘制。作为决定其中数字重要的结果，它们被分为多个层次。基于所需精度的参考，进一步确定预定级别，将其分类为高于预定级别的精度，并且通过数据处理执行低于预定级别的精度。如果重要的数字只是整体的一小部分，与整个芯片在多模式下绘制相比，该方法以更高的速度进行。剩下的不太重要的数字可以使用较少的通行模式绘制。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2011081786A Modeling and simulating device mismatch for designing integrated circuit 有权
标题翻译：用于设计集成电路的建模和仿真器件错配
公开(公告)号：JP2011081786A
公开(公告)日：2011-04-21
申请号：JP2010205642
申请日：2010-09-14
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズ, インコーポレイテッド
发明人： O'RIORDAN DONALD J , SCHALDENBRAND ARTHUR , O'DONOVAN JOHN
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5068 , G06F17/504 , G06F17/5072 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： PROBLEM TO BE SOLVED: To allow a user to specify layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. SOLUTION: The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：允许用户为电路原理图中的设备指定布局样式，其中布局样式捕获设备布置和设备相关性的特征。
解决方案：可以通过使用计算机来模拟结果布局，以便可以对电路评估一个或多个性能指标。在某些情况下，可以使用测试芯片来确定对应于不同布局样式的布置的设备相关性。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2005026537A Integrated circuit and method for layout thereof 有权
标题翻译：集成电路及其布局方法
公开(公告)号：JP2005026537A
公开(公告)日：2005-01-27
申请号：JP2003191693
申请日：2003-07-04
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： TATEISHI KAZUYUKI
IPC分类号： G06F17/50 , H01L21/82 , H03K19/195
摘要： PROBLEM TO BE SOLVED: To provide a layout method by which area efficiency is improved by simplifying wiring of a data transmission route, a clock transmission route, etc. for facilitating layout work while securing fast operation in an integrated circuit using an SFQ circuit in particular.
SOLUTION: P is set to the position of the junction of a clock, α to the position of the logic cell of a poststage (second logic cell), and β to the position of the logic cell of a prestage (first logic cell). A condition (1) is that a virtual rectangle (including a square) where P and α are positioned at vertexes opposing each other across a diagonal line is supposed, and β is arranged inside of the rectangle. A condition (2) is that a route from P to α, a route from P to β and a route from β to α are selected to be respectively a Manhattan distance. Then the positions and routes of P, α and β are decided so as to satisfy the conditions (1) and (2). By layout like this, wiring is simplified while keeping fast operation, and the area efficiency is improved.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过简化数据传输路由的布线，时钟传输路由等来提高面积效率的布局方法，以便于在使用SFQ的集成电路中确保快速操作的同时进行布局工作电路特别。解决方案：将P设置为时钟的结点α与后级（第二逻辑单元）的逻辑单元的位置，并将β设置为前级逻辑单元的位置（第一逻辑细胞）。假设条件（1）是其中P和α位于对角线上彼此相对的顶点处的虚拟矩形（包括正方形），并且β被布置在矩形内部。条件（2）是从P到α的路由，从P到β的路由和从β到α的路由被选择为分别是曼哈顿距离。然后确定P，α和β的位置和路线以满足条件（1）和（2）。通过这样的布局，简化了接线，同时保持快速运行，提高了面积效率。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2009266237A Peak power detection in digital designs using emulation systems 审中-公开
标题翻译：使用仿真系统进行数字设计中的峰值功率检测
公开(公告)号：JP2009266237A
公开(公告)日：2009-11-12
申请号：JP2009123564
申请日：2009-04-24
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： ZHU BING , LIN TSAIR-CHIN , TUNG TUNG-SUN , GAO JINGBO
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/78
摘要： PROBLEM TO BE SOLVED: To provide a technique concerning use of a function verification system. SOLUTION: A method of analyzing power consumption for a DUT (Device Under Test) includes a step of providing emulation data for states of the DUT in one or more time windows, a step of determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in one or more time windows, a step of dividing each time window into one or more segments based on at least one power criterion, a step of determining power-activity values for the one or more segments, a step of determining power-consumption values for the one or more segments from the power-activity values, a step of using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in one or more time windows, and a step of saving one or more values for power activity of the DUT in a computer-readable medium. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用功能验证系统的技术。解决方案：分析DUT（被测器件）功耗的方法包括在一个或多个时间窗口中提供DUT状态的仿真数据的步骤，从仿真数据确定操作模式值的步骤，以及选择表征一个或多个时间窗口中的电路行为的操作模式，基于至少一个功率标准将每个时间窗分成一个或多个段的步骤;确定一个或多个段的功率活动值的步骤从所述功率活动值确定所述一个或多个区段的功率消耗值的步骤;使用所述功率活动值和所述功耗值来确定所述一个或多个区段的相对功率活动并调整所述一个或多个段以一个或多个时间窗口中的操作模式为目标的高功率活动，以及在计算机可读介质中保存DUT的功率活动的一个或多个值的步骤。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009087376A Method and apparatus for interconnection 审中-公开
标题翻译：用于互连的方法和装置
公开(公告)号：JP2009087376A
公开(公告)日：2009-04-23
申请号：JP2009005831
申请日：2009-01-14
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： HE LIMIN , YAO SO-ZEN , DENG WENYONG , CHEN JING , CHAO LIANG-JIH
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5077
摘要： PROBLEM TO BE SOLVED: To provide a routing method for an integrated circuit design layout.
SOLUTION: The layout can include design netlists and library cells. A multiple-level global routing can generate a topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供集成电路设计布局的布线方法。
解决方案：布局可以包括设计网表和库单元格。多级全局路由可以为每个网络生成拓扑线。可以执行设计上面向图形的基于图形的详细路由。可以执行详细路由后的路由优化，以进一步提高路由质量。一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2009076073A Method and apparatus for statistical evaluation of embedded software execution time 审中-公开
标题翻译：嵌入式软件执行时间统计评估的方法与装置
公开(公告)号：JP2009076073A
公开(公告)日：2009-04-09
申请号：JP2008239668
申请日：2008-09-18
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： MARTIN GRANT E , GIUSTO PAOLO
IPC分类号： G06F11/34 , G06F9/44 , G06F11/28 , G06F11/30 , G06F11/36
CPC分类号： G06F11/3447 , G06F11/3428 , G06F11/3457 , G06F2201/815 , G06F2201/865
摘要： PROBLEM TO BE SOLVED: To provide an estimating device for estimating software execution times.
SOLUTION: A method for statistically estimating software execution times is implemented by preparing a model of a target processor based on a set of benchmark programs, correlating the software to be estimated to the benchmark programs, applying the correlated software to the model and determining the estimated values of software execution times. The model is developed by determining the actual execution times of the benchmark programs, determining a number of virtual instructions in the benchmark programs and determining a predictor equation that correlates the virtual instructions to the actual execution times. The predictor equation is determined by making a correlation analysis of the virtual instructions, excluding highly correlated instructions, and executing a combination of stepwise linear regression and multiple linear regression.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供用于估计软件执行时间的估计装置。解决方案：一种用于统计估计软件执行时间的方法是通过基于一组基准程序准备一个目标处理器的模型来实现的，将要估计的软件与基准程序相关联，将相关软件应用于模型，确定软件执行时间的估计值。该模型通过确定基准程序的实际执行时间，确定基准程序中的虚拟指令数量并确定将虚拟指令与实际执行时间相关联的预测器方程来开发。通过对虚拟指令进行相关分析，排除高度相关的指令，并执行逐步线性回归和多元线性回归的组合来确定预测因子方程式。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2007293871A Hardware emulation system having heterogeneous cluster of processor 有权
标题翻译：具有处理器异质集群的硬件仿真系统
公开(公告)号：JP2007293871A
公开(公告)日：2007-11-08
申请号：JP2007127373
申请日：2007-04-11
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： BERSHTEYN MIKHAIL , POPLACK MITCHELL G , ELMUFDI BESHARA G
IPC分类号： G06F17/50 , G06F11/22 , G06F11/28
CPC分类号： G06F17/5027
摘要： PROBLEM TO BE SOLVED: To provide a heterogeneous processor based hardware emulation system. SOLUTION: A hardware emulation system having a heterogeneous cluster of processors is described. An apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises a step for using a data fetch processor to retrieve data from a data array, a step for evaluating the retrieved data using the data fetch processor to produce an output bit, a step for supplying the output bit to an intracluster crossbar, and a step for using a data store processor to store the output bit in the data array. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供基于异构处理器的硬件仿真系统。描述了具有异构的处理器簇的硬件仿真系统。用于模拟硬件设计的装置包括多个处理器，其中每个处理器在仿真周期期间执行不同的功能。由该装置执行的方法包括使用数据提取处理器从数据阵列检索数据的步骤，使用数据获取处理器来评估检索的数据以产生输出位的步骤，将输出位提供给集群内交叉开关，以及使用数据存储处理器将输出位存储在数据阵列中的步骤。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2013077844A Local preferred direction architecture, tools and apparatus 审中-公开
标题翻译：本地优选方向架构，工具和装置
公开(公告)号：JP2013077844A
公开(公告)日：2013-04-25
申请号：JP2013007856
申请日：2013-01-18
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： ASMUS HETZEL , ANISH MALHOTRA , FUJIMURA AKI , JACQUES ETIENNE , JON FRANKLE , DAVID S HARRISON , HEATH FEATHER , ALEXANDER MATVEEV , KING ROGER
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5077
摘要： PROBLEM TO BE SOLVED: To provide an apparatus for routing a net using a "local preferred direction (LPD)" wiring model.SOLUTION: An LPD wiring model for use with one or more EDA tools (such as placing, routing, etc.,) is provided. The LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set.
摘要翻译：要解决的问题：提供一种使用“本地优选方向（LPD）”布线模型布线网络的装置。
解决方案：提供了一种用于一个或多个EDA工具（如放置，布线等）的LPD接线模型。 LPD布线模型允许至少一个布线层具有各自具有与特定布线层不同的优选方向的一组区域。此外，每个区域具有局部优选方向，其不同于该组中至少一个其它区域的局部优选方向。此外，至少两个区域具有两个不同的多边形形状，并且该集合中的区域不包含该组中的另一区域。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2010092470A Method implemented by machine for implementing compact manufacturing model during various stages of electronic circuit design 审中-公开
标题翻译：在电子电路设计各个阶段实施紧凑型制造机器的机器实现的方法
公开(公告)号：JP2010092470A
公开(公告)日：2010-04-22
申请号：JP2009221919
申请日：2009-09-28
申请人： Cadence Design Systems Inc , ケイデンスデザインシステムズインコーポレイテッド
发明人： SONG LI J , DODDI SRINI , DREGE EMMANUEL , JAKATDAR NICKHIL
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068
摘要： PROBLEM TO BE SOLVED: To disclose a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. SOLUTION: In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：公开在电子电路设计的各个阶段中实现紧凑型制造模型的方法，系统和计算机程序产品。解决方案：在一些实施例中，该方法或系统接收或识别基于物理的数据。在一些实施例中，该方法或系统通过使用金制造过程模型来接收或识别相应制造过程的基于物理的数据。在一些实施例中，该方法或系统使用基于物理的数据来微调，修改或调整黄金制造过程模型。在一些实施例中，该方法或系统调用正确的模块。在一些实施例中，该方法或系统实现紧凑的制造模型和逐个设计模块，并为电子电路设计的各个阶段提供指导。版权所有（C）2010，JPO＆INPIT

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