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    • 9. 发明申请
    • EFFICIENT EVENT FILTER
    • 高效过滤器
    • WO2015044630A1
    • 2015-04-02
    • PCT/GB2014/000379
    • 2014-09-24
    • BRITISH TELECOMMUNICATIONS PLC
    • AZVINE, BehnamMARTIN, Trevor Philip
    • G06F9/54G06F11/30G06F21/55G06F9/44
    • G06F9/4881G06F8/30G06F9/542G06F11/3072G06F21/552G06F2201/86
    • A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimised such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising: a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the code sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification; a virtual machine adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph.
    • 一种包括处理器的序列识别装置,其中所述装置适于在多个时间有序事件中识别的事件序列中访问事件等价类别的有向非循环图数据结构,并且其中所述图被优化为使得初始和最终 在图中组合具有公共等价类的事件序列的子序列,该装置包括:代码生成器,适于生成与图形相对应的可执行代码,使得代码包括用于图的每个事件分类的指令序列,代码 事件分类的顺序适于评估标准以确定事件是否对应于事件分类; 适于执行生成的可执行代码的虚拟机,使得在使用中,可执行代码基于该图来过滤输入的时间有序的事件。
    • 10. 发明申请
    • METHOD AND DEVICES FOR FREQUENCY DISTRIBUTION
    • 用于频率分配的方法和设备
    • WO2015036721A1
    • 2015-03-19
    • PCT/GB2013/052374
    • 2013-09-11
    • KHALIFA UNIVERSITY OF SCIENCE, TECHNOLOGY, AND RESEARCHBRITISH TELECOMMUNICATIONS PLCEMIRATES TELECOMMUNICATIONS CORPORATION
    • AWEYA, JamesAL SINDI, NayefAL-ZUBAIDI, Saeed
    • H04J3/06
    • H04J3/0664H04J3/0667
    • This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).
    • 本发明涉及基于例如IEEE 1588精确时间协议(PTP)的用于频率分布的方法和装置。 分组延迟变化(PDV)是恢复时钟中的噪声的直接贡献者,并且已经提出了各种技术来减轻其影响。 本发明的实施例提供了一种在从时钟处直接测量和去除时钟恢复机制中的PDV效应的机制。 一个具体实施例提供了一种时钟恢复机制,其包括具有内置PDV补偿特征的锁相环(PLL)。 本发明的目的是使从时钟将主时钟恢复到更高的质量,就好像主机和从机之间的通信路径没有PDV一样。 该技术可以允许分组网络提供与时分复用(TDM)网络和全球定位系统(GPS)相同级别的时钟同步服务。