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1. 发明授权

US08379185B2 Liquid crystal display device with repairable structure 有权
标题翻译：具有可修复结构的液晶显示装置
公开(公告)号：US08379185B2
公开(公告)日：2013-02-19
申请号：US12777692
申请日：2010-05-11
申请人： Yuan-Hao Chang , Chien-Ming Chen
发明人： Yuan-Hao Chang , Chien-Ming Chen
IPC分类号： G02F1/13
CPC分类号： G02F1/136259 , G02F2001/136263
摘要： The present invention discloses a liquid crystal display device with repairable structure, including a glass substrate; a wire structure formed on the glass substrate, wherein the wire structure includes one or a plurality of through holes formed therein; a dielectric layer formed on the wire structure and the glass substrate; and a plurality of pixel electrodes formed on the dielectric layer, wherein one or more gaps are formed between the plurality of pixel electrodes and the position of the gaps aligns with the position of the through holes.
摘要翻译：本发明公开了一种具有可修复结构的液晶显示装置，包括玻璃基板; 形成在所述玻璃基板上的线结构，其中所述线结构包括形成在其中的一个或多个通孔; 形成在所述导线结构和所述玻璃基板上的电介质层; 以及形成在所述电介质层上的多个像素电极，其中在所述多个像素电极之间形成一个或多个间隙，并且所述间隙的位置与所述通孔的位置对准。

2. 发明授权

US08305506B2 Pixel set 有权
标题翻译：像素集
公开(公告)号：US08305506B2
公开(公告)日：2012-11-06
申请号：US12550410
申请日：2009-08-31
申请人： Yuan-Hao Chang , Huei-Chung Yu , Yi-Chen Chiu
发明人： Yuan-Hao Chang , Huei-Chung Yu , Yi-Chen Chiu
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213 , G02F1/136286
摘要： A pixel set including two scan lines parallel to each other, a data line intersected with the scan lines, and two pixels located between the scan lines is provided. The pixels are at two sides of the data line, respectively. Each pixel includes an active device disposed adjacent to the data line, a pixel electrode, a storage capacitance electrode partially overlapped with the pixel electrode, and a drain compensating pattern including a branch. The branch is located at a side of the pixel electrode away from the data line, and has a concavity located at a side of the branch adjacent to the data line. The drain compensating pattern is connected to a drain of the active device. A portion of the drain compensating pattern is located inside the concavity. The branch is not overlapped with the drain compensating pattern at a side of the concavity away from the gate.
摘要翻译：提供了包括彼此平行的两条扫描线，与扫描线相交的数据线以及位于扫描线之间的两个像素的像素组。像素分别位于数据线的两侧。每个像素包括与数据线相邻设置的有源器件，像素电极，与像素电极部分重叠的存储电容电极和包括分支的漏极补偿图案。分支位于像素电极的远离数据线的一侧，并且具有位于与数据线相邻的分支侧的凹面。漏极补偿图案连接到有源器件的漏极。漏极补偿图案的一部分位于凹部内部。分支不与漏极补偿图案重叠在凹口的远离栅极的一侧。

3. 发明申请

US20110161563A1 BLOCK MANAGEMENT METHOD OF A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的块管理方法
公开(公告)号：US20110161563A1
公开(公告)日：2011-06-30
申请号：US12702254
申请日：2010-02-08
申请人： Yuan-Hao Chang , Tei-Wei Kuo
发明人： Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F12/02 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0246 , G06F11/1441 , G06F2212/7205
摘要： A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets.
摘要翻译：提供了适用于非易失性存储器存储系统的块管理方法。非易失性存储器存储系统包括多个芯片。每个芯片包括多个物理块。物理块形成多个物理块集合。逻辑空间中的每个逻辑块对应于至多两个物理块集合。在块管理方法中，当逻辑块对应于填充有数据的两个物理块集合并且要写入更多数据时，分配用于存储数据的空闲物理块集合。然后，根据预定的标准来选择对应于逻辑块的两个物理块集合中的一个。所选物理块集合中的有效数据被复制到空闲物理块集中。接下来，所选择的物理块集被擦除并收集到空闲的物理块集合池中。

4. 发明申请

US20090256986A1 PIXEL STRUCTURE AND REPAIRING METHOD THEREOF 审中-公开
标题翻译：像素结构及其修复方法
公开(公告)号：US20090256986A1
公开(公告)日：2009-10-15
申请号：US12334511
申请日：2008-12-14
申请人： Chien-Ming Chen , Yuan-Hao Chang
发明人： Chien-Ming Chen , Yuan-Hao Chang
IPC分类号： G02F1/133 , G02F1/13
CPC分类号： G02F1/136259
摘要： A pixel structure includes a scan line, a gate, a common line, a first dielectric layer, a channel layer, a source, a drain, a data line, a capacitance coupling electrode (CCE), a second dielectric layer and a pixel electrode. The gate, the common line and the scan line are disposed on the substrate, and the gate is electrically connected to the scan line. The common line has at least one first opening, and at least a portion of the first opening is located between the data line and the CCE. The channel layer is disposed on the first dielectric layer above the gate. The source and the drain are disposed on the channel layer. The CCE is disposed on the first dielectric layer above the common line and electrically connected to the drain. The pixel electrode is disposed on the second dielectric layer, and electrically connected to the CCE.
摘要翻译：像素结构包括扫描线，栅极，公共线，第一介电层，沟道层，源极，漏极，数据线，电容耦合电极（CCE），第二电介质层和像素电极。栅极，公共线和扫描线设置在基板上，并且栅极电连接到扫描线。公共线具有至少一个第一开口，并且第一开口的至少一部分位于数据线和CCE之间。沟道层设置在栅极上方的第一介电层上。源极和漏极设置在沟道层上。 CCE设置在公共线上方的第一电介质层上并电连接到漏极。像素电极设置在第二电介质层上，并与CCE电连接。

5. 发明申请

US20070030408A1 LIQUID CRYSTAL DISPLAY PANEL, THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DETECTION METHODS THEREFOR 审中-公开
标题翻译：液晶显示面板，薄膜晶体管阵列基板及其检测方法
公开(公告)号：US20070030408A1
公开(公告)日：2007-02-08
申请号：US11161531
申请日：2005-08-08
申请人： Kuang-Hsiang Lin , Yuan-Hao Chang
发明人： Kuang-Hsiang Lin , Yuan-Hao Chang
IPC分类号： G02F1/1333
CPC分类号： G02F1/136204 , G02F1/1309
摘要： A thin film transistor (TFT) array substrate including a substrate, pixel units, scan and data lines, inner anti-static rings, first and second thin film transistors is provided. The pixel units are arranged on a display region of the substrate, and the scan and data lines are arranged on the substrate. Each pixel unit is controlled by the corresponding scan and data line. The inner anti-static rings, the first and second TFTs are arranged on a peripheral circuit region of the substrate around the display region. The gate and source of each first TFT are connected to one part of the inner anti-static ring, and the drain of each first TFT is connected to the scan line respectively. The gate and source of each second TFT are connected to the other part of the inner anti-static ring, and the drain of each second TFT is connected to the data line respectively.
摘要翻译：提供了包括基板，像素单元，扫描和数据线，内部防静电环，第一和第二薄膜晶体管的薄膜晶体管（TFT）阵列基板。像素单元布置在基板的显示区域上，扫描和数据线布置在基板上。每个像素单元由相应的扫描和数据线控制。内部防静电环，第一和第二TFT布置在显示区域周围的基板的外围电路区域上。每个第一TFT的栅极和源极连接到内部防静电环的一部分，并且每个第一TFT的漏极分别连接到扫描线。每个第二TFT的栅极和源极连接到内部防静电环的另一部分，并且每个第二TFT的漏极分别连接到数据线。

6. 发明申请

US20100275146A1 System and method for managing devices in an information handling system 审中-公开
标题翻译：用于管理信息处理系统中的设备的系统和方法
公开(公告)号：US20100275146A1
公开(公告)日：2010-10-28
申请号：US12429365
申请日：2009-04-24
申请人： Hsien-Pao Sun , Yu-Fu Kuo , Che-Kuan Chiu , Yuan-Hao Chang
发明人： Hsien-Pao Sun , Yu-Fu Kuo , Che-Kuan Chiu , Yuan-Hao Chang
IPC分类号： G06F3/048
CPC分类号： G06Q10/10
摘要： An information handling system stores code, layout information, and location information in a memory. A processor executes the code to read the information, render a representation of the information handling system from the layout information, and display the representation on a display. The representation includes a connector that is located based on the location information. A method includes displaying a representation of an information handling system and a device. The representation includes depictions of the information handling system and the device. The method also includes receiving an input selecting the depiction of the device, and disabling the device in response to receiving the input. A memory includes code for carrying out the method.
摘要翻译：信息处理系统将代码，布局信息和位置信息存储在存储器中。处理器执行代码以读取信息，从布局信息呈现信息处理系统的表示，并在显示器上显示该表示。该表示包括基于位置信息定位的连接器。一种方法包括显示信息处理系统和设备的表示。该表示包括描述信息处理系统和设备。所述方法还包括接收选择所述设备的描绘的输入，以及响应于接收到所述输入来禁用所述设备。存储器包括用于执行该方法的代码。

7. 发明申请

US20100002164A1 PIXEL STRUCTURES AND FABRICATING METHODS THEREOF 有权
标题翻译：像素结构及其制作方法
公开(公告)号：US20100002164A1
公开(公告)日：2010-01-07
申请号：US12241048
申请日：2008-09-30
申请人： Chia-Ming Chiang , Yuan-Hao Chang , Hsi-Ming Chang
发明人： Chia-Ming Chiang , Yuan-Hao Chang , Hsi-Ming Chang
IPC分类号： G02F1/1368 , H01L31/0232
CPC分类号： G02F1/1368 , H01L27/124
摘要： A fabricating method of a pixel structure is provided, which uses the original processes of fabricating a thin film transistor to simultaneously fabricate a reflective layer with an uneven surface. In the fabrication process of the thin film transistor, a plurality of bumps are formed under the reflective layer which is to be formed later on. The bumps and a gate of the TFT are formed simultaneously or the bumps and a semiconductor layer of the TFT are formed simultaneously. In addition, by stacking layers on the bumps, the reflective layer formed on the bumps can have good uneven shapes on the surface thereon. Therefore, the fabricating method of a pixel structure has simple processes and low manufacturing costs, and can be used for fabricating a transflective pixel structure or a reflective pixel structure.
摘要翻译：提供了一种像素结构的制造方法，其使用制造薄膜晶体管的原始工艺来同时制造具有不平坦表面的反射层。在薄膜晶体管的制造工艺中，在稍后形成的反射层下方形成多个凸块。 TFT的突起和栅极同时形成，或者同时形成突起和TFT的半导体层。此外，通过在凸块上堆叠层，形成在凸块上的反射层在其上的表面上可以具有良好的不均匀形状。因此，像素结构的制造方法具有简单的工艺和低制造成本，并且可以用于制造透反射像素结构或反射像素结构。

8. 发明授权

US07461198B2 System and method for configuration and management of flash memory 有权
公开(公告)号：US07461198B2
公开(公告)日：2008-12-02
申请号：US11490049
申请日：2006-07-21
申请人： Yi-Lin Tsai , Tei-Wei Kuo , Jen-Wei Hsieh , Yuan-Hao Chang , Hsiang-Chi Hsieh
发明人： Yi-Lin Tsai , Tei-Wei Kuo , Jen-Wei Hsieh , Yuan-Hao Chang , Hsiang-Chi Hsieh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0246
摘要： A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory.

9. 发明申请

US20080043161A1 Thin film transistor array substrate and liquid crystal display devices 有权
标题翻译：薄膜晶体管阵列基板和液晶显示装置
公开(公告)号：US20080043161A1
公开(公告)日：2008-02-21
申请号：US11594851
申请日：2006-11-09
申请人： Meng-Chi Liou , Yuan-Hao Chang
发明人： Meng-Chi Liou , Yuan-Hao Chang
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213
摘要： A thin film transistor array substrate applied to a liquid crystal display device is provided with at least two storage capacitance lines electrically connected with each other. These electrically connected storage capacitance lines, which belong to two adjacent pixels at two sides of a scanning line, are connected with contact holes and conductive layer, and may eliminate the lateral crosstalk of the liquid crystal display device.
摘要翻译：应用于液晶显示装置的薄膜晶体管阵列基板具有彼此电连接的至少两个辅助电容线。属于扫描线两侧的两个相邻像素的这些电连接的存储电容线与接触孔和导电层连接，并且可以消除液晶显示装置的横向串扰。

10. 发明申请

US20060256246A1 Thin film transistor array 有权
公开(公告)号：US20060256246A1
公开(公告)日：2006-11-16
申请号：US11197821
申请日：2005-08-05
申请人： Ming-Zen Wu , Yuan-Hao Chang
发明人： Ming-Zen Wu , Yuan-Hao Chang
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213 , G02F2001/13606
摘要： A thin film transistor array comprises a substrate, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of common-used distributed lines and a plurality of auxiliary electrodes, wherein the thin film transistors, the pixel electrodes and the auxiliary electrodes are respectively disposed in each exposure shot formed on the substrate. A first overlapped area exists between drains and gates so as to form parasitic capacitances between the sources and the gates. Each auxiliary electrode is disposed under the pixel electrodes and extends over the common-used distributed lines along the direction to its one side. A second overlapped area exists between the auxiliary electrodes and the common-used distributed lines so as to form storage capacitances between each auxiliary electrode and its corresponding common-used distributed line.

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