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    • 6. 发明授权
    • Liquid crystal display apparatus
    • 液晶显示装置
    • US06300996B1
    • 2001-10-09
    • US09321454
    • 1999-05-27
    • Hiroaki MatsuyamaKazumi KobayashiYoshihiko HiraiToshiya IshiiHideya MuraiMasayoshi Suzuki
    • Hiroaki MatsuyamaKazumi KobayashiYoshihiko HiraiToshiya IshiiHideya MuraiMasayoshi Suzuki
    • G02F11343
    • G02F1/134336G02F1/133707G02F2001/13373
    • A liquid crystal display device can suppress pixel-based gradation fluctuations observed upon change in angle of view with increased size as it meets wide angle of view characteristics required of a large-sized liquid crystal display device. A device in which a liquid crystal material is sealed between a pair of substrates 31, 32, a plurality of pixel electrodes 38 for applying voltage across the liquid crystal material is arranged on the substrate 31, a common electrode 12 for applying a voltage common to the pixel electrodes 38 is arranged on the substrate 32, and in which a gate line 22 and a drain line 23 of a switching element adapted to control the voltage applied across the pixel electrodes 38 are provided for extending substantially at right angles to each other. In the device, orientation of the liquid crystal molecules 18 neighboring to the pixel electrode 38 is perpendicular to that of liquid crystal molecules 19 neighboring to the common electrode 12, while the respective orientations are substantially parallel to the direction of the gate line 22 or that of the drain line 23.
    • 液晶显示装置可以抑制视大小变化而观察到的像素级的色调波动,因为其符合大尺寸液晶显示装置所需的广视角特性。 将液晶材料密封在一对基板31,32之间的装置,在液晶材料上施加多个用于施加电压的像素电极38设置在基板31上,公共电极12用于施加与 像素电极38被布置在衬底32上,并且其中设置适于控制施加在像素电极38两端的电压的开关元件的栅极线22和漏极线23用于彼此基本成直角地延伸。 在该器件中,与像素电极38相邻的液晶分子18的取向垂直于与公共电极12相邻的液晶分子19的取向,而各取向基本上平行于栅极线22的方向,或者 的排水管路23。
    • 8. 发明授权
    • Resonance tunnel device
    • 共振隧道装置
    • US6015978A
    • 2000-01-18
    • US175505
    • 1998-10-20
    • Koichiro YukiKiyoyuki MoritaKiyoshi MorimotoYoshihiko Hirai
    • Koichiro YukiKiyoyuki MoritaKiyoshi MorimotoYoshihiko Hirai
    • H01L21/306H01L21/329H01L29/88H01L29/06
    • H01L29/6609H01L21/30608H01L29/882Y10S438/962
    • The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
    • 形成本发明的半导体微结构的方法包括以下步骤:在具有半导体层作为其上部的衬底上形成具有第一开口和第二开口的掩模图案; 以及使用所述掩模图案选择性地蚀刻所述半导体层,以形成在平行于所述基板的表面的第一方向上延伸的半导体微结构,其中,在选择性地蚀刻所述半导体层的步骤中,沿垂直于所述基板的第二方向的蚀刻速率 第一方向并平行于衬底的表面相对于第一方向上的蚀刻速率基本上为零,并且半导体微结构的宽度基本上等于第一开口和第二开口在第二方向上的最短距离 。